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/Linux-v6.6/Documentation/devicetree/bindings/media/
Dqcom,sm8250-camss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Robert Foss <robert.foss@linaro.org>
18 const: qcom,sm8250-camss
24 clock-names:
26 - const: cam_ahb_clk
27 - const: cam_hf_axi
28 - const: cam_sf_axi
[all …]
Dti,cal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benoit Parrot <bparrot@ti.com>
12 description: |-
15 processing capability to connect CSI2 image-sensor modules to the
24 - ti,dra72-cal
26 - ti,dra72-pre-es2-cal
28 - ti,dra76-cal
30 - ti,am654-cal
[all …]
Dcdns,csi2rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MIPI-CSI2 RX controller
10 - Maxime Ripard <mripard@kernel.org>
13 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
14 lanes in input, and 4 different pixel streams in output.
19 - enum:
20 - starfive,jh7110-csi2rx
21 - const: cdns,csi2rx
[all …]
Dvideo-interfaces.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/video-interfaces.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
29 #address-cells = <1>;
30 #size-cells = <0>;
45 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
49 specify #address-cells, #size-cells properties independently for the 'port'
[all …]
Drockchip-isp1.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Helen Koike <helen.koike@collabora.com>
19 - rockchip,px30-cif-isp
20 - rockchip,rk3399-cif-isp
29 interrupt-names:
31 - const: isp
32 - const: mi
[all …]
Drenesas,rzg2l-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
21 - enum:
22 - renesas,r9a07g044-csi2 # RZ/G2{L,LC}
[all …]
Dqcom,msm8996-camss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Robert Foss <robert.foss@linaro.org>
12 - Todor Tomov <todor.too@gmail.com>
19 const: qcom,msm8996-camss
25 clock-names:
27 - const: top_ahb
28 - const: ispif_ahb
[all …]
/Linux-v6.6/arch/arm64/boot/dts/renesas/
Dr8a779a0-falcon-csi-dsi.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CSI/DSI sub-board
8 #include <dt-bindings/media/video-interfaces.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-lanes = <0>;
22 data-lanes = <1 2 3 4>;
23 remote-endpoint = <&max96712_out0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
[all …]
Dhihope-rzg2-ex-aistarvision-mipi-adapter-2.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
10 #include "aistarvision-mipi-adapter-2.1.dtsi"
18 clock-lanes = <0>;
19 data-lanes = <1 2>;
20 remote-endpoint = <&ov5645_ep>;
32 clock-lanes = <0>;
33 data-lanes = <1 2>;
34 remote-endpoint = <&imx219_ep>;
41 pinctrl-0 = <&i2c3_pins>;
42 pinctrl-names = "default";
[all …]
Dr8a779g0-white-hawk-csi-dsi.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board
8 #include <dt-bindings/media/video-interfaces.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
21 bus-type = <MEDIA_BUS_TYPE_CSI2_CPHY>;
22 clock-lanes = <0>;
23 data-lanes = <1 2 3>;
24 remote-endpoint = <&max96712_out0>;
34 #address-cells = <1>;
[all …]
Dr8a774c0-ek874-mipi-2.1.dts1 // SPDX-License-Identifier: GPL-2.0
4 * connected with aistarvision-mipi-v2-adapter board
9 /dts-v1/;
10 #include "r8a774c0-ek874.dts"
13 #include "aistarvision-mipi-adapter-2.1.dtsi"
16 …model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-ada…
17 compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0";
38 clock-lanes = <0>;
39 data-lanes = <1 2>;
40 remote-endpoint = <&ov5645_ep>;
[all …]
Drz-smarc-cru-csi-ov5645.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "regulator-fixed";
12 regulator-name = "camera_vdddo";
13 regulator-min-microvolt = <1800000>;
14 regulator-max-microvolt = <1800000>;
15 regulator-always-on;
19 compatible = "regulator-fixed";
20 regulator-name = "camera_vdda";
21 regulator-min-microvolt = <2800000>;
22 regulator-max-microvolt = <2800000>;
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/media/i2c/
Dadv748x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kieran Bingham <kieran.bingham@ideasonboard.com>
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
15 HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
21 - enum:
22 - adi,adv7481
23 - adi,adv7482
29 The ADV748x has up to twelve 256-byte maps that can be accessed via the
[all …]
Dovti,ov7251.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
15 - Todor Tomov <todor.too@gmail.com>
25 description: XCLK Input Clock
27 clock-names:
30 clock-frequency:
31 description: Frequency of the xclk clock in Hz.
33 vdda-supply:
[all …]
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
8 - compatible: value should be "toshiba,tc358743"
9 - clocks, clock-names: should contain a phandle link to the reference clock
10 source, the clock input is named "refclk".
14 - reset-gpios: gpio phandle GPIO connected to the reset pin
15 - interrupts: GPIO connected to the interrupt pin
16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/phy/
Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
[all …]
Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
[all …]
/Linux-v6.6/drivers/media/i2c/
Dccs-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
[all …]
/Linux-v6.6/drivers/gpu/drm/tegra/
Ddp.c1 // SPDX-License-Identifier: MIT
3 * Copyright (C) 2013-2019 NVIDIA Corporation
17 caps->enhanced_framing = false; in drm_dp_link_caps_reset()
18 caps->tps3_supported = false; in drm_dp_link_caps_reset()
19 caps->fast_training = false; in drm_dp_link_caps_reset()
20 caps->channel_coding = false; in drm_dp_link_caps_reset()
21 caps->alternate_scrambler_reset = false; in drm_dp_link_caps_reset()
27 dest->enhanced_framing = src->enhanced_framing; in drm_dp_link_caps_copy()
28 dest->tps3_supported = src->tps3_supported; in drm_dp_link_caps_copy()
29 dest->fast_training = src->fast_training; in drm_dp_link_caps_copy()
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/display/ti/
Dti,omap5-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/pci/
Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
/Linux-v6.6/drivers/gpu/drm/renesas/rcar-du/
Drzg2l_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0
45 unsigned int lanes; member
165 iowrite32(data, dsi->mmio + reg); in rzg2l_mipi_dsi_phy_write()
170 iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg); in rzg2l_mipi_dsi_link_write()
175 return ioread32(dsi->mmio + reg); in rzg2l_mipi_dsi_phy_read()
180 return ioread32(dsi->mmio + LINK_REG_OFFSET + reg); in rzg2l_mipi_dsi_link_read()
183 /* -----------------------------------------------------------------------------
202 if (hsfreq <= dphy_timings->hsfreq_max) in rzg2l_mipi_dsi_dphy_init()
218 DSIDPHYTIM0_T_INIT(dphy_timings->t_init); in rzg2l_mipi_dsi_dphy_init()
219 dphytim1 = DSIDPHYTIM1_THS_PREPARE(dphy_timings->ths_prepare) | in rzg2l_mipi_dsi_dphy_init()
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/display/bridge/
Drenesas,dsi-csi2-tx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
15 to four data lanes.
20 - renesas,r8a779a0-dsi-csi2-tx # for V3U
[all …]

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