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/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 dma_ipg_clk: clock-dma-ipg {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
Dimx8-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 lsio_mem_clk: clock-lsio-mem {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
Dimx8-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 conn_axi_clk: clock-conn-axi {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
Dimx8-ss-audio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 audio_ipg_clk: clock-audio-ipg {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
Dimx8-ss-img.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
7 compatible = "simple-bus";
8 #address-cells = <1>;
9 #size-cells = <1>;
12 img_ipg_clk: clock-img-ipg {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <200000000>;
16 clock-output-names = "img_ipg_clk";
[all …]
Dimx8dxl-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
18 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
20 interrupt-parent = <&gic>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
14 model to control the clock gates for the peripherals. An LPCG module
17 This level of clock gating is provided after the clocks are generated
18 by the SCU resources and clock controls. Thus even if the clock is
[all …]
Dallwinner,sun4i-a10-gates-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Bus Gates Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 This additional argument passed to that clock is the offset of
24 - const: allwinner,sun4i-a10-gates-clk
[all …]
Drenesas,cpg-mstp-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
18 and the clock index in the group, from 0 to 31.
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
[all …]
Dallwinner,sun8i-h3-bus-gates-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Bus Gates Clock
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 This additional argument passed to that clock is the offset of
23 const: allwinner,sun8i-h3-bus-gates-clk
[all …]
Dstarfive,jh7100-audclk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Audio Clock Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7100-audclk
21 - description: Audio source clock
22 - description: External 12.288MHz clock
23 - description: Domain 7 AHB bus clock
[all …]
Dstarfive,jh7100-clkgen.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Clock Generator
10 - Geert Uytterhoeven <geert@linux-m68k.org>
11 - Emil Renner Berthing <kernel@esmil.dk>
15 const: starfive,jh7100-clkgen
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/firmware/
Darm,scpi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
33 - const: arm,scpi # SCPI v1.0 and above
34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
35 - items:
36 - enum:
37 - amlogic,meson-gxbb-scpi
38 - const: arm,scpi-pre-1.0
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dr7s72100.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <dt-bindings/clock/r7s72100-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
[all …]
Ddm816x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
[all …]
Dr8a7740.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
Dsh73a0.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
Dr8a7778.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
[all …]
/Linux-v6.1/drivers/clk/sunxi/
Dclk-sun8i-bus-gates.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on clk-simple-gates.c, which is:
8 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/clk-provider.h>
41 int idx = of_property_match_string(node, "clock-names", in sun8i_h3_bus_gates_init()
53 number = of_property_count_u32_elems(node, "clock-indices"); in sun8i_h3_bus_gates_init()
54 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sun8i_h3_bus_gates_init()
56 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sun8i_h3_bus_gates_init()
57 if (!clk_data->clks) in sun8i_h3_bus_gates_init()
61 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sun8i_h3_bus_gates_init()
[all …]
Dclk-simple-gates.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 #include <linux/clk-provider.h>
43 number = of_property_count_u32_elems(node, "clock-indices"); in sunxi_simple_gates_setup()
44 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sunxi_simple_gates_setup()
46 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
47 if (!clk_data->clks) in sunxi_simple_gates_setup()
50 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sunxi_simple_gates_setup()
51 of_property_read_string_index(node, "clock-output-names", in sunxi_simple_gates_setup()
57 clk_data->clks[index] = clk_register_gate(NULL, clk_name, in sunxi_simple_gates_setup()
[all …]
/Linux-v6.1/drivers/clk/imx/
Dclk-imx8qxp-lpcg.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
18 #include "clk-scu.h"
19 #include "clk-imx8qxp-lpcg.h"
21 #include <dt-bindings/clock/imx8-clock.h>
24 * struct imx8qxp_lpcg_data - Description of one LPCG clock
25 * @id: clock ID
26 * @name: clock name
27 * @parent: parent clock name
28 * @flags: common clock flags
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/serial/
Dnxp,sc16is7xx.txt1 * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
5 - compatible: Should be one of the following:
6 - "nxp,sc16is740" for NXP SC16IS740,
7 - "nxp,sc16is741" for NXP SC16IS741,
8 - "nxp,sc16is750" for NXP SC16IS750,
9 - "nxp,sc16is752" for NXP SC16IS752,
10 - "nxp,sc16is760" for NXP SC16IS760,
11 - "nxp,sc16is762" for NXP SC16IS762.
12 - reg: I2C address of the SC16IS7xx device.
13 - interrupts: Should contain the UART interrupt
[all …]
/Linux-v6.1/drivers/clk/renesas/
Dclk-mstp.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
25 * status register when enabling the clock.
31 * struct mstp_clock_group - MSTP gating clocks group
33 * @data: clock specifier translation for clocks in this group
37 * @width_8bit: registers are 8-bit, not 32-bit
50 * struct mstp_clock - MSTP gating clock
51 * @hw: handle between common and hardware-specific interfaces
66 return group->width_8bit ? readb(reg) : readl(reg); in cpg_mstp_read()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/rtc/
Dmaxim,ds3231.txt1 * Maxim DS3231 Real Time Clock
4 - compatible: Should contain "maxim,ds3231".
5 - reg: I2C address for chip.
8 - #clock-cells: Should be 1.
9 - clock-output-names:
10 overwrite the default clock names "ds3231_clk_sqw" and "ds3231_clk_32khz".
12 Each clock is assigned an identifier and client nodes can use this identifier
13 to specify the clock which they consume. Following indices are allowed:
14 - 0: square-wave output on the SQW pin
15 - 1: square-wave output on the 32kHz pin
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/ti/
Dfapll.txt1 Binding for Texas Instruments FAPLL clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped FAPLL with usually two selectable input clocks
7 (reference clock and bypass clock), and one or more child
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - compatible : shall be "ti,dm816-fapll-clock"
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
16 - reg : address and length of the register set for controlling the FAPLL.
[all …]

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