| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-gates-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Bus Gates Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 This additional argument passed to that clock is the offset of
24 - const: allwinner,sun4i-a10-gates-clk
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| D | renesas,cpg-mstp-clocks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
18 and the clock index in the group, from 0 to 31.
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
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| D | allwinner,sun8i-h3-bus-gates-clk.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun8i-h3-bus-gates-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Bus Gates Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 This additional argument passed to that clock is the offset of
23 const: allwinner,sun8i-h3-bus-gates-clk
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| D | clock-bindings.txt | 1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
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| D | st,stm32mp1-rcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Reset Clock Controller Binding
10 - Gabriel Fernandez <gabriel.fernandez@st.com>
13 The RCC IP is both a reset and a clock controller.
17 This binding uses common clock bindings
18 Documentation/devicetree/bindings/clock/clock-bindings.txt
24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device
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| D | maxim,max77686.txt | 1 Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
4 multi-function device. More information can be found in MFD DT binding
10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
12 dt-bindings/clock/maxim,max77686.h.
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
17 dt-bindings/clock/maxim,max77802.h.
19 The MAX77686 contains one 32.768khz clock outputs that can be controlled
21 dt-bindings/clock/maxim,max77620.h.
27 - #clock-cells: from common clock binding; shall be set to 1.
30 - clock-output-names: From common clock binding.
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | arm,scpi.txt | 2 ----------------------------------------------------------
10 - compatible : should be
12 * "arm,scpi-pre-1.0" : For implementations complying to all
14 - mboxes: List of phandle and mailbox channel specifiers
17 - shmem : List of phandle pointing to the shared memory(SHM) area between the
26 Clock bindings for the clocks based on SCPI Message Protocol
27 ------------------------------------------------------------
29 This binding uses the common clock binding[1].
34 - compatible : should be "arm,scpi-clocks"
36 protocol much be listed as sub-nodes under this node.
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | r7s72100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 #include <dt-bindings/clock/r7s72100-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
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| D | dm816x-clocks.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
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| D | r8a7740.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
8 #include <dt-bindings/clock/r8a7740-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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| D | sh73a0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
8 #include <dt-bindings/clock/sh73a0-clock.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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| D | r8a7778.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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| /Linux-v5.10/drivers/clk/sunxi/ |
| D | clk-sun8i-bus-gates.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on clk-simple-gates.c, which is:
8 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/clk-provider.h>
41 int idx = of_property_match_string(node, "clock-names", in sun8i_h3_bus_gates_init()
53 number = of_property_count_u32_elems(node, "clock-indices"); in sun8i_h3_bus_gates_init()
54 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sun8i_h3_bus_gates_init()
56 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sun8i_h3_bus_gates_init()
57 if (!clk_data->clks) in sun8i_h3_bus_gates_init()
61 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sun8i_h3_bus_gates_init()
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| D | clk-simple-gates.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 #include <linux/clk-provider.h>
43 number = of_property_count_u32_elems(node, "clock-indices"); in sunxi_simple_gates_setup()
44 of_property_read_u32_index(node, "clock-indices", number - 1, &number); in sunxi_simple_gates_setup()
46 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); in sunxi_simple_gates_setup()
47 if (!clk_data->clks) in sunxi_simple_gates_setup()
50 of_property_for_each_u32(node, "clock-indices", prop, p, index) { in sunxi_simple_gates_setup()
51 of_property_read_string_index(node, "clock-output-names", in sunxi_simple_gates_setup()
57 clk_data->clks[index] = clk_register_gate(NULL, clk_name, in sunxi_simple_gates_setup()
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| /Linux-v5.10/Documentation/devicetree/bindings/serial/ |
| D | nxp,sc16is7xx.txt | 1 * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART)
5 - compatible: Should be one of the following:
6 - "nxp,sc16is740" for NXP SC16IS740,
7 - "nxp,sc16is741" for NXP SC16IS741,
8 - "nxp,sc16is750" for NXP SC16IS750,
9 - "nxp,sc16is752" for NXP SC16IS752,
10 - "nxp,sc16is760" for NXP SC16IS760,
11 - "nxp,sc16is762" for NXP SC16IS762.
12 - reg: I2C address of the SC16IS7xx device.
13 - interrupts: Should contain the UART interrupt
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| /Linux-v5.10/drivers/clk/renesas/ |
| D | clk-mstp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
25 * status register when enabling the clock.
31 * struct mstp_clock_group - MSTP gating clocks group
33 * @data: clock specifier translation for clocks in this group
37 * @width_8bit: registers are 8-bit, not 32-bit
50 * struct mstp_clock - MSTP gating clock
51 * @hw: handle between common and hardware-specific interfaces
66 return group->width_8bit ? readb(reg) : readl(reg); in cpg_mstp_read()
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| D | clk-div6.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_shift: Shift to access the register bits to select the parent clock
32 * @src_width: Number of register bits to select the parent clock (may be 0)
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| /Linux-v5.10/Documentation/devicetree/bindings/rtc/ |
| D | maxim,ds3231.txt | 1 * Maxim DS3231 Real Time Clock
4 - compatible: Should contain "maxim,ds3231".
5 - reg: I2C address for chip.
8 - #clock-cells: Should be 1.
9 - clock-output-names:
10 overwrite the default clock names "ds3231_clk_sqw" and "ds3231_clk_32khz".
12 Each clock is assigned an identifier and client nodes can use this identifier
13 to specify the clock which they consume. Following indices are allowed:
14 - 0: square-wave output on the SQW pin
15 - 1: square-wave output on the 32kHz pin
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ti/ |
| D | fapll.txt | 1 Binding for Texas Instruments FAPLL clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped FAPLL with usually two selectable input clocks
7 (reference clock and bypass clock), and one or more child
10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 - compatible : shall be "ti,dm816-fapll-clock"
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
16 - reg : address and length of the register set for controlling the FAPLL.
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| /Linux-v5.10/include/dt-bindings/clock/ |
| D | s3c2410.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Device Tree binding constants clock controllers of Samsung S3C2410 and later.
12 * Let each exported clock get a unique index, which is used on DT-enabled
13 * platforms to lookup the clock from a clock specifier. These indices are
15 * that new clocks should be added either in free spaces between clock groups
30 /* pclk-gates */
45 /* hclk-gates */
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| D | s3c2412.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Device Tree binding constants clock controllers of Samsung S3C2412.
12 * Let each exported clock get a unique index, which is used on DT-enabled
13 * platforms to lookup the clock from a clock specifier. These indices are
15 * that new clocks should be added either in free spaces between clock groups
40 /* pclk-gates */
55 /* hclk-gates */
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| D | s3c2443.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
12 * Let each exported clock get a unique index, which is used on DT-enabled
13 * platforms to lookup the clock from a clock specifier. These indices are
15 * that new clocks should be added either in free spaces between clock groups
46 /* hclk-gates */
67 /* pclk-gates */
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| /Linux-v5.10/drivers/clk/meson/ |
| D | g12a-aoclk.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
13 * These indices are entirely contrived and do not map onto the hardware.
15 * include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want
29 #include <dt-bindings/clock/g12a-aoclkc.h>
30 #include <dt-bindings/reset/g12a-aoclkc.h>
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| /Linux-v5.10/Documentation/devicetree/bindings/media/ |
| D | ti,omap3isp.txt | 4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
22 cam_xclka and cam_xclkb, at indices 0 and 1,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
30 video-interfaces.txt in the same directory.
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| /Linux-v5.10/drivers/gpu/drm/savage/ |
| D | savage_state.c | 1 /* savage_state.c -- State and drawing support for Savage
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
39 uint32_t scstart = dev_priv->state.s3d.new_scstart; in savage_emit_clip_rect_s3d()
40 uint32_t scend = dev_priv->state.s3d.new_scend; in savage_emit_clip_rect_s3d()
42 ((uint32_t) pbox->x1 & 0x000007ff) | in savage_emit_clip_rect_s3d()
43 (((uint32_t) pbox->y1 << 16) & 0x07ff0000); in savage_emit_clip_rect_s3d()
45 (((uint32_t) pbox->x2 - 1) & 0x000007ff) | in savage_emit_clip_rect_s3d()
46 ((((uint32_t) pbox->y2 - 1) << 16) & 0x07ff0000); in savage_emit_clip_rect_s3d()
47 if (scstart != dev_priv->state.s3d.scstart || in savage_emit_clip_rect_s3d()
48 scend != dev_priv->state.s3d.scend) { in savage_emit_clip_rect_s3d()
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