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/Linux-v6.1/Documentation/devicetree/bindings/i2c/
Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dbcm11351.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012-2013 Broadcom Corporation
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
7 #include "dt-bindings/clock/bcm281xx.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <0>;
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Dbcm23550.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
37 #include "dt-bindings/clock/bcm21664.h"
40 #address-cells = <1>;
41 #size-cells = <1>;
44 interrupt-parent = <&gic>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a7";
54 clock-frequency = <1000000000>;
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Daxm5516-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/boot/dts/axm5516-cpus.dtsi
10 #address-cells = <1>;
11 #size-cells = <0>;
13 cpu-map {
74 compatible = "arm,cortex-a15";
76 clock-frequency = <1400000000>;
77 cpu-release-addr = <0>; // Fixed by the boot loader
82 compatible = "arm,cortex-a15";
84 clock-frequency = <1400000000>;
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Dbcm21664.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
7 #include "dt-bindings/clock/bcm21664.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-a9";
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Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 clock@60006000 {
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
14 timing-20400000 {
15 clock-frequency = <20400000>;
[all …]
Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
8 clock@60006000 {
9 emc-timings-1 {
10 nvidia,ram-code = <1>;
12 timing-12750000 {
13 clock-frequency = <12750000>;
14 nvidia,parent-clock-frequency = <408000000>;
16 clock-names = "emc-parent";
19 timing-20400000 {
[all …]
Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 clock@60006000 {
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
14 timing-20400000 {
15 clock-frequency = <20400000>;
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Dsocfpga_vt.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
11 compatible = "altr,socfpga-vt", "altr,socfpga";
27 clock-frequency = <10000000>;
33 broken-cd;
34 bus-width = <4>;
35 cap-mmc-highspeed;
36 cap-sd-highspeed;
40 phy-mode = "gmii";
45 clock-frequency = <7000000>;
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/Linux-v6.1/drivers/media/i2c/
Dccs-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
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/Linux-v6.1/arch/arm64/boot/dts/amd/
Damd-seattle-clks.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
12 clock-output-names = "adl3clk_100mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <375000000>;
19 clock-output-names = "ccpclk_375mhz";
23 compatible = "fixed-clock";
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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
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Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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Dsilabs,si570.txt2 I2C clock generators.
5 This binding uses the common clock binding[1]. Details about the devices can be
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
15 - compatible: Shall be one of "silabs,si570", "silabs,si571",
17 - reg: I2C device address.
18 - #clock-cells: From common clock bindings: Shall be 0.
19 - factory-fout: Factory set default frequency. This frequency is part specific.
20 The correct frequency for the part used has to be provided in
23 - temperature-stability: Temperature stability of the device in PPM. Should be
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/Linux-v6.1/Documentation/devicetree/bindings/display/exynos/
Dexynos_dsim.txt4 - compatible: value should be one of the following
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
10 - reg: physical base address and length of the registers set for the device
11 - interrupts: should contain DSI interrupt
12 - clocks: list of clock specifiers, must contain an entry for each required
13 entry in clock-names
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/Linux-v6.1/arch/nios2/boot/dts/
D10m50_devboard.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
10 compatible = "altr,niosii-max10";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "altr,nios2-1.1";
22 interrupt-controller;
23 #interrupt-cells = <1>;
[all …]
/Linux-v6.1/arch/arc/boot/dts/
Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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/Linux-v6.1/arch/arm64/boot/dts/arm/
Djuno-clocks.dtsi4 * Copyright (c) 2013-2014 ARM Ltd
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <7372800>;
15 clock-output-names = "juno:uartclk";
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <48000000>;
22 clock-output-names = "clk48mhz";
26 compatible = "fixed-clock";
[all …]
/Linux-v6.1/drivers/staging/sm750fb/
Dddk750_chip.c1 // SPDX-License-Identifier: GPL-2.0
52 * This function set up the main chip clock.
54 * Input: Frequency to be set.
56 static void set_chip_clock(unsigned int frequency) in set_chip_clock() argument
60 /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ in set_chip_clock()
64 if (frequency) { in set_chip_clock()
68 pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in set_chip_clock()
74 * up the exact clock required by the User. in set_chip_clock()
76 * possible clock. in set_chip_clock()
78 sm750_calc_pll_value(frequency, &pll); in set_chip_clock()
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/Linux-v6.1/drivers/clk/
Dclk-si570.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (C) 2011 - 2021 Xilinx Inc.
14 #include <linux/clk-provider.h>
54 * @hw: Clock hw struct
57 * @max_freq: Maximum frequency for this device
58 * @fxtal: Factory xtal frequency
59 * @n1: Clock divider N1
60 * @hs_div: Clock divider HSDIV
61 * @rfreq: Clock multiplier RFREQ
62 * @frequency: Current output frequency
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/wireless/
Dti,wlcore.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 Note that the *-clock-frequency properties assume internal clocks. In case
15 of external clocks, new bindings (for parsing the clock nodes) have to be
21 - ti,wl1271
22 - ti,wl1273
23 - ti,wl1281
24 - ti,wl1283
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/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
21 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
26 clock-names:
28 - const: dmc_clk
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/Linux-v6.1/drivers/clk/pxa/
Dclk-pxa2xx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 #define CCCR (0x0000) /* Core Clock Configuration Register */
6 #define CCSR (0x000C) /* Core Clock Status Register */
7 #define CKEN (0x0004) /* Clock Enable Register */
10 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
11 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
12 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
25 #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
26 #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
27 #define CKEN_MEMC (22) /* Memory Controller Clock Enable */
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/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-driver-habanalabs21 Description: Allows the user to set the maximum clock frequency, in MHz.
22 The device clock might be set to lower value than the maximum.
24 frequency value of the device clock. This property is valid
31 Description: Displays the current frequency, in MHz, of the device clock.
64 on-board EEPROM
82 Description: Interface to trigger a hard-reset operation for the device.
83 Hard-reset will reset ALL internal components of the device
90 Description: Displays how many times the device have undergone a hard-reset
97 Description: Allows the user to set the maximum clock frequency for MME, TPC
105 Description: Allows the user to set the maximum clock frequency, in Hz, of
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/Linux-v6.1/Documentation/devicetree/bindings/media/i2c/
Daptina,mt9p031.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
15 simple two-wire serial interface.
20 - aptina,mt9p006
21 - aptina,mt9p031
22 - aptina,mt9p031m
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