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/Linux-v5.10/arch/arm/boot/dts/
Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for DRA7xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
[all …]
Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM43xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
12 ti,bit-shift = <31>;
17 #clock-cells = <0>;
18 compatible = "ti,mux-clock";
20 ti,bit-shift = <29>;
25 #clock-cells = <0>;
26 compatible = "ti,mux-clock";
[all …]
Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for AM33xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
12 ti,bit-shift = <22>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <1>;
25 #clock-cells = <0>;
[all …]
Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <12000000>;
15 #clock-cells = <0>;
16 compatible = "ti,gate-clock";
18 ti,bit-shift = <8>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
[all …]
Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <59000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <12000000>;
21 #clock-cells = <0>;
22 compatible = "ti,gate-clock";
[all …]
Domap36xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-no-wait-gate-clock";
12 ti,bit-shift = <0>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-divider-clock";
20 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
[all …]
Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
[all …]
Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
[all …]
Ddm816x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
[all …]
/Linux-v5.10/drivers/clk/berlin/
Dberlin2-div.c1 // SPDX-License-Identifier: GPL-2.0
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
9 #include <linux/clk-provider.h>
16 #include "berlin2-div.h"
19 * Clock dividers in Berlin2 SoCs comprise a complex cell to select
23 * +---+
24 * pll0 --------------->| 0 | +---+
25 * +---+ |(B)|--+--------------->| 0 | +---+
26 * pll1.0 -->| 0 | +-->| 1 | | +--------+ |(E)|----->| 0 | +---+
27 * pll1.1 -->| 1 | | +---+ +-->|(C) 1:M |-->| 1 | |(F)|-->|(G)|->
[all …]
/Linux-v5.10/drivers/clk/
Dclk-divider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Adjustable divider clock implementation
10 #include <linux/clk-provider.h>
19 * DOC: basic adjustable divider clock that cannot gate
21 * Traits of this clock:
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
25 * parent - fixed parent. No clk_set_parent support
[all …]
Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
15 * Traits of this clock:
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
[all …]
/Linux-v5.10/drivers/clk/zynqmp/
Ddivider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
18 * Traits of this clock:
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
[all …]
/Linux-v5.10/drivers/clk/renesas/
Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-gen3-cpg.h"
32 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
63 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
67 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
[all …]
Dclk-div6.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7790 Common Clock Framework support
10 #include <linux/clk-provider.h>
20 #include "clk-div6.h"
27 * struct div6_clock - CPG 6 bit divider clock
28 * @hw: handle between common and hardware-specific interfaces
29 * @reg: IO-remapped register
30 * @div: divisor value (1-64)
31 * @src_shift: Shift to access the register bits to select the parent clock
32 * @src_width: Number of register bits to select the parent clock (may be 0)
[all …]
/Linux-v5.10/drivers/clk/sunxi/
Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
[all …]
/Linux-v5.10/drivers/media/i2c/
Daptina-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "aptina-pll.h"
25 unsigned int div; in aptina_pll_calculate() local
27 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
28 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
30 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
31 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
32 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
33 return -EINVAL; in aptina_pll_calculate()
36 if (pll->pix_clock == 0 || pll->pix_clock > limits->pix_clock_max) { in aptina_pll_calculate()
[all …]
/Linux-v5.10/drivers/clk/bcm/
Dclk-kona-setup.c18 #include "clk-kona.h"
21 #define selector_clear_exists(sel) ((sel)->width = 0)
28 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
31 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
34 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
37 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
40 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
43 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
53 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
55 struct bcm_clk_div *div; in clk_requires_trigger() local
[all …]
Dclk-kona.c15 #include "clk-kona.h"
20 #include <linux/clk-provider.h>
35 /* Produces a mask of set bits covering a range of a 32-bit value */
38 return ((1 << width) - 1) << shift; in bitfield_mask()
58 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div) in scaled_div_value() argument
60 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
68 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths) in scaled_div_build() argument
76 combined <<= div->u.s.frac_width; in scaled_div_build()
83 scaled_div_min(struct bcm_clk_div *div) in scaled_div_min() argument
85 if (divider_is_fixed(div)) in scaled_div_min()
[all …]
/Linux-v5.10/drivers/clk/ti/
Ddivider.c2 * TI Divider Clock
6 * Tero Kristo <t-kristo@ti.com>
18 #include <linux/clk-provider.h>
24 #include "clock.h"
34 for (clkt = table; clkt->div; clkt++) in _get_table_div()
35 if (clkt->val == val) in _get_table_div()
36 return clkt->div; in _get_table_div()
46 if (divider->table) { in _setup_mask()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
50 if (clkt->val > max_val) in _setup_mask()
[all …]
/Linux-v5.10/drivers/mmc/host/
Dsdhci-cns3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "sdhci-pltfm.h"
23 static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock) in sdhci_cns3xxx_set_clock() argument
25 struct device *dev = mmc_dev(host->mmc); in sdhci_cns3xxx_set_clock()
26 int div = 1; in sdhci_cns3xxx_set_clock() local
30 host->mmc->actual_clock = 0; in sdhci_cns3xxx_set_clock()
34 if (clock == 0) in sdhci_cns3xxx_set_clock()
37 while (host->max_clk / div > clock) { in sdhci_cns3xxx_set_clock()
42 if (div < 4) in sdhci_cns3xxx_set_clock()
43 div += 1; in sdhci_cns3xxx_set_clock()
[all …]
/Linux-v5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-clock.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/clock/bcm-sr.h>
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 #clock-cells = <0>;
43 compatible = "fixed-factor-clock";
45 clock-div = <2>;
46 clock-mult = <1>;
50 #clock-cells = <1>;
[all …]
/Linux-v5.10/drivers/clk/ingenic/
Dcgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2013-2015 Imagination Technologies
11 #include <linux/clk-provider.h>
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
38 * Retrieves the state of the clock gate bit described by info. The
39 * caller must hold cgu->lock.
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
48 ^ info->clear_to_gate; in ingenic_cgu_gate_get()
52 * ingenic_cgu_gate_set() - set the value of clock gate register bit
[all …]
/Linux-v5.10/drivers/clk/mvebu/
Dclk-corediv.c1 // SPDX-License-Identifier: GPL-2.0
3 * MVEBU Core divider clock
7 * Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
12 #include <linux/clk-provider.h>
23 * to configure one particular core divider clock. Those hardware
37 * array of core divider clock descriptors for this SoC, as well as
50 * This structure represents one core divider clock for the clock
51 * framework, and is dynamically allocated for each core divider clock
70 { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */
74 { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
[all …]
/Linux-v5.10/sound/aoa/soundbus/i2sbus/
Dinterface.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * i2sbus driver -- interface register definitions
61 * - clock source
62 * - MClk divisor
63 * - SClk divisor
64 * - SClk master flag
65 * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
66 * - external sample frequency interrupt (don't understand)
67 * - external sample frequency
70 /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
[all …]

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