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/Linux-v6.1/drivers/clk/ti/
Dclk-7xx.c44 …{ DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:…
129 { DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
130 { DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
131 { DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
132 { DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
133 { DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
135 { DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
215 "atl-clkctrl:0000:24",
226 { DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
302 { DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
[all …]
Dclk-44xx.c59 "abe-clkctrl:0018:26",
79 "abe-clkctrl:0020:26",
92 "abe-clkctrl:0028:26",
105 "abe-clkctrl:0030:26",
118 "abe-clkctrl:0038:26",
186 { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
188 { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
189 { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
190 { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
191 { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
[all …]
Dclk-54xx.c53 "abe-clkctrl:0018:26",
73 "abe-clkctrl:0028:26",
86 "abe-clkctrl:0030:26",
99 "abe-clkctrl:0038:26",
139 { OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
141 { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
142 { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
143 { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
144 { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
145 { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
[all …]
Dclk-33xx.c19 "clk-24mhz-clkctrl:0000:0",
151 "l3-aon-clkctrl:0000:19",
152 "l3-aon-clkctrl:0000:30",
157 "l3-aon-clkctrl:0000:20",
167 "l3-aon-clkctrl:0000:22",
192 { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
207 { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
241 DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
243 DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
244 DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
[all …]
Dclk-43xx.c35 …{ AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4-wkup-aon-clkctrl…
256 DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0148:8"),
257 DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0058:8"),
258 DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0060:8"),
259 DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:0068:8"),
260 DT_CLK(NULL, "gpio4_dbclk", "l4ls-clkctrl:0070:8"),
261 DT_CLK(NULL, "gpio5_dbclk", "l4ls-clkctrl:0078:8"),
262 DT_CLK(NULL, "synctimer_32kclk", "l4-wkup-aon-clkctrl:0008:8"),
263 DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l3s-clkctrl:01f8:8"),
264 DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3s-clkctrl:0200:8"),
[all …]
Dclkctrl.c3 * OMAP clkctrl clock support
249 /* Get clkctrl clock base name based on clkctrl_name or dts node */
257 /* l4per-clkctrl:1234:0 style naming based on clkctrl_name */ in clkctrl_get_clock_name()
259 clock_name = kasprintf(GFP_KERNEL, "%s-clkctrl:%04x:%d", in clkctrl_get_clock_name()
276 /* l4per-clkctrl:1234:0 style naming based on node name */ in clkctrl_get_clock_name()
465 * compatible property for clkctrl.
490 if (!strncmp("ti,clkctrl-", compat, prefix_len)) { in clkctrl_get_name()
574 pr_err("%pOF not found from clkctrl data.\n", node); in _ti_omap4_clkctrl_setup()
593 * The code below can be removed when all clkctrl nodes use domain in _ti_omap4_clkctrl_setup()
711 CLK_OF_DECLARE(ti_omap4_clkctrl_clock, "ti,clkctrl",
[all …]
DMakefile8 clkctrl.o
Dclock.h75 /* CLKCTRL flags */
160 /* CLKCTRL type definitions */
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dti-clkctrl.txt1 Texas Instruments clkctrl clock binding
3 Texas Instruments SoCs can have a clkctrl clock controller for each
4 interconnect target module. The clkctrl clock controller manages functional
5 and interface clocks for each module. Each clkctrl controller can also
7 or more clock muxes. There is a clkctrl clock controller typically for each
10 The clock consumers can specify the index of the clkctrl clock using
11 the hardware offset from the clkctrl instance register space. The optional
12 clocks can be specified by clkctrl hardware offset and the index of the
19 - compatible : shall be "ti,clkctrl" or a clock domain specific name:
20 "ti,clkctrl-l4-cfg"
[all …]
Dartpec6.txt19 See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
20 - compatible: Should be "axis,artpec6-clkctrl"
35 clkctrl: clkctrl@f8000000 {
37 compatible = "axis,artpec6-clkctrl";
Dimx23-clock.yaml64 const: fsl,imx23-clkctrl
82 compatible = "fsl,imx23-clkctrl";
Dimx28-clock.yaml87 const: fsl,imx28-clkctrl
105 compatible = "fsl,imx28-clkctrl";
/Linux-v6.1/drivers/clk/mxs/
Dclk-imx28.c17 static void __iomem *clkctrl; variable
18 #define CLKCTRL clkctrl macro
20 #define PLL0CTRL0 (CLKCTRL + 0x0000)
21 #define PLL1CTRL0 (CLKCTRL + 0x0020)
22 #define PLL2CTRL0 (CLKCTRL + 0x0040)
23 #define CPU (CLKCTRL + 0x0050)
24 #define HBUS (CLKCTRL + 0x0060)
25 #define XBUS (CLKCTRL + 0x0070)
26 #define XTAL (CLKCTRL + 0x0080)
27 #define SSP0 (CLKCTRL + 0x0090)
[all …]
Dclk-imx23.c16 static void __iomem *clkctrl; variable
19 #define CLKCTRL clkctrl macro
22 #define PLLCTRL0 (CLKCTRL + 0x0000)
23 #define CPU (CLKCTRL + 0x0020)
24 #define HBUS (CLKCTRL + 0x0030)
25 #define XBUS (CLKCTRL + 0x0040)
26 #define XTAL (CLKCTRL + 0x0050)
27 #define PIX (CLKCTRL + 0x0060)
28 #define SSP (CLKCTRL + 0x0070)
29 #define GPMI (CLKCTRL + 0x0080)
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dartpec6.dtsi45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
103 clkctrl: clkctrl@f8000000 { label
105 compatible = "axis,artpec6-clkctrl";
115 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
122 clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>;
259 clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
281 clocks = <&clkctrl ARTPEC6_CLK_DMA_ACLK>;
289 clocks = <&clkctrl ARTPEC6_CLK_ETH_ACLK>,
290 <&clkctrl ARTPEC6_CLK_PTP_REF>;
335 clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>,
[all …]
Dam33xx-clocks.dtsi630 compatible = "ti,clkctrl";
637 compatible = "ti,clkctrl";
644 compatible = "ti,clkctrl";
651 compatible = "ti,clkctrl";
658 compatible = "ti,clkctrl";
665 compatible = "ti,clkctrl";
672 compatible = "ti,clkctrl";
679 compatible = "ti,clkctrl";
695 compatible = "ti,clkctrl";
702 compatible = "ti,clkctrl";
[all …]
Domap44xx-clocks.dtsi1161 compatible = "ti,clkctrl";
1177 compatible = "ti,clkctrl";
1193 compatible = "ti,clkctrl";
1212 compatible = "ti,clkctrl";
1228 compatible = "ti,clkctrl";
1244 compatible = "ti,clkctrl";
1260 compatible = "ti,clkctrl";
1276 compatible = "ti,clkctrl";
1292 compatible = "ti,clkctrl";
1308 compatible = "ti,clkctrl";
[all …]
Ddra7xx-clocks.dtsi1708 compatible = "ti,clkctrl";
1725 compatible = "ti,clkctrl";
1742 compatible = "ti,clkctrl";
1751 compatible = "ti,clkctrl";
1768 compatible = "ti,clkctrl";
1785 compatible = "ti,clkctrl";
1801 compatible = "ti,clkctrl";
1820 compatible = "ti,clkctrl";
1836 compatible = "ti,clkctrl";
1853 compatible = "ti,clkctrl";
[all …]
Domap54xx-clocks.dtsi1109 compatible = "ti,clkctrl";
1125 compatible = "ti,clkctrl";
1141 compatible = "ti,clkctrl";
1160 compatible = "ti,clkctrl";
1176 compatible = "ti,clkctrl";
1192 compatible = "ti,clkctrl";
1208 compatible = "ti,clkctrl";
1224 compatible = "ti,clkctrl";
1240 compatible = "ti,clkctrl";
1256 compatible = "ti,clkctrl";
[all …]
Dam43xx-clocks.dtsi875 compatible = "ti,clkctrl";
882 compatible = "ti,clkctrl";
889 compatible = "ti,clkctrl";
906 compatible = "ti,clkctrl";
922 compatible = "ti,clkctrl";
938 compatible = "ti,clkctrl";
954 compatible = "ti,clkctrl";
961 compatible = "ti,clkctrl";
968 compatible = "ti,clkctrl";
975 compatible = "ti,clkctrl";
[all …]
Ddm814x-clocks.dtsi346 compatible = "ti,clkctrl";
360 compatible = "ti,clkctrl";
374 compatible = "ti,clkctrl";
Ddm816x-clocks.dtsi257 compatible = "ti,clkctrl";
271 compatible = "ti,clkctrl";
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dmediatek,mt7621-pcie.yaml109 clocks = <&clkctrl 24>;
124 clocks = <&clkctrl 25>;
139 clocks = <&clkctrl 26>;
/Linux-v6.1/arch/arm/mach-cns3xxx/
Dcore.c97 u32 clkctrl; in cns3xxx_power_off() local
101 clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET); in cns3xxx_power_off()
102 clkctrl &= 0xfffff1ff; in cns3xxx_power_off()
103 clkctrl |= (0x5 << 9); /* Hibernate */ in cns3xxx_power_off()
104 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); in cns3xxx_power_off()
/Linux-v6.1/drivers/clk/axis/
Dclk-artpec6.c15 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
113 CLK_OF_DECLARE_DRIVER(artpec6_clkctrl, "axis,artpec6-clkctrl",
227 { .compatible = "axis,artpec6-clkctrl" },

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