| /Linux-v5.10/include/dt-bindings/clock/ |
| D | exynos5410.h | 36 #define CLK_UART0 257 macro
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| D | actions,s500-cmu.h | 58 #define CLK_UART0 38 macro
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| D | actions,s700-cmu.h | 58 #define CLK_UART0 36 macro
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| D | actions,s900-cmu.h | 85 #define CLK_UART0 67 macro
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| D | pistachio-clk.h | 39 #define CLK_UART0 48 macro
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| D | exynos5250.h | 92 #define CLK_UART0 289 macro
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| D | s5pv210.h | 161 #define CLK_UART0 143 macro
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| D | exynos5420.h | 66 #define CLK_UART0 257 macro
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| D | exynos4.h | 150 #define CLK_UART0 312 macro
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| D | exynos3250.h | 222 #define CLK_UART0 216 macro
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| D | sprd,sc9860-clk.h | 85 #define CLK_UART0 2 macro
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | exynos5410-clock.txt | 48 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| D | exynos3250-clock.txt | 55 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
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| /Linux-v5.10/Documentation/devicetree/bindings/serial/ |
| D | sprd-uart.yaml | 71 clocks = <&clk_ap_apb_gates 9>, <&clk_uart0>, <&ext_26m>;
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| /Linux-v5.10/drivers/clk/zte/ |
| D | clk-zx296702.c | 46 #define CLK_UART0 (lsp1crpm_base + 0x20) macro
688 ARRAY_SIZE(uart_wclk_sel), CLK_UART0, 4, 1); in zx296702_lsp1_clocks_init()
692 zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31); in zx296702_lsp1_clocks_init()
694 zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0); in zx296702_lsp1_clocks_init()
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| /Linux-v5.10/drivers/clk/actions/ |
| D | owl-s700.c | 279 static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
442 &clk_uart0.common,
525 [CLK_UART0] = &clk_uart0.common.hw,
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| /Linux-v5.10/drivers/clk/sirf/ |
| D | clk-atlas6.c | 82 &clk_uart0.hw,
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| D | clk-prima2.c | 81 &clk_uart0.hw,
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| /Linux-v5.10/drivers/clk/hisilicon/ |
| D | clk-hi3519.c | 58 { HI3519_UART0_CLK, "clk_uart0", "24m",
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| D | crg-hi3516cv300.c | 87 { HI3516CV300_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
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| /Linux-v5.10/arch/arm64/boot/dts/actions/ |
| D | s700.dtsi | 119 clocks = <&cmu CLK_UART0>;
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| D | s900.dtsi | 125 clocks = <&cmu CLK_UART0>;
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | s5pv210.dtsi | 324 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
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| D | exynos5410.dtsi | 344 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| /Linux-v5.10/arch/arm64/boot/dts/sprd/ |
| D | whale2.dtsi | 80 <&ap_clk CLK_UART0>, <&ext_26m>;
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