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/Linux-v5.4/drivers/clk/ux500/
Du8500_of_clk.c11 #include <linux/clk-provider.h>
13 #include "clk.h"
18 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
19 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
20 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
[all …]
/Linux-v5.4/arch/c6x/platforms/
Dpll.c16 #include <linux/clk.h>
27 static void __clk_enable(struct clk *clk) in __clk_enable() argument
29 if (clk->parent) in __clk_enable()
30 __clk_enable(clk->parent); in __clk_enable()
31 clk->usecount++; in __clk_enable()
34 static void __clk_disable(struct clk *clk) in __clk_disable() argument
36 if (WARN_ON(clk->usecount == 0)) in __clk_disable()
38 --clk->usecount; in __clk_disable()
40 if (clk->parent) in __clk_disable()
41 __clk_disable(clk->parent); in __clk_disable()
[all …]
/Linux-v5.4/drivers/media/v4l2-core/
Dv4l2-clk.c9 #include <linux/clk.h>
19 #include <media/v4l2-clk.h>
27 struct v4l2_clk *clk; in v4l2_clk_find() local
29 list_for_each_entry(clk, &clk_list, list) in v4l2_clk_find()
30 if (!strcmp(dev_id, clk->dev_id)) in v4l2_clk_find()
31 return clk; in v4l2_clk_find()
38 struct v4l2_clk *clk; in v4l2_clk_get() local
39 struct clk *ccf_clk = clk_get(dev, id); in v4l2_clk_get()
46 clk = kzalloc(sizeof(*clk), GFP_KERNEL); in v4l2_clk_get()
47 if (!clk) { in v4l2_clk_get()
[all …]
/Linux-v5.4/drivers/clk/imx/
Dclk-imx27.c2 #include <linux/clk.h>
3 #include <linux/clk-provider.h>
14 #include "clk.h"
49 static struct clk *clk[IMX27_CLK_MAX]; variable
52 static struct clk ** const uart_clks[] __initconst = {
53 &clk[IMX27_CLK_PER1_GATE],
54 &clk[IMX27_CLK_UART1_IPG_GATE],
55 &clk[IMX27_CLK_UART2_IPG_GATE],
56 &clk[IMX27_CLK_UART3_IPG_GATE],
57 &clk[IMX27_CLK_UART4_IPG_GATE],
[all …]
Dclk-imx5.c7 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
19 #include "clk.h"
128 static struct clk *clk[IMX5_CLK_END]; variable
131 static struct clk ** const uart_clks_mx51[] __initconst = {
132 &clk[IMX5_CLK_UART1_IPG_GATE],
133 &clk[IMX5_CLK_UART1_PER_GATE],
134 &clk[IMX5_CLK_UART2_IPG_GATE],
135 &clk[IMX5_CLK_UART2_PER_GATE],
136 &clk[IMX5_CLK_UART3_IPG_GATE],
[all …]
Dclk-vf610.c7 #include <linux/clk.h>
11 #include "clk.h"
112 static struct clk *clk[VF610_CLK_END]; variable
130 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
133 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
136 if (IS_ERR(clk)) in vf610_get_fixed_clock()
137 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
138 return clk; in vf610_get_fixed_clock()
183 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
184 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
[all …]
Dclk-imx31.c7 #include <linux/clk.h>
17 #include "clk.h"
51 static struct clk *clk[clk_max]; variable
54 static struct clk ** const uart_clks[] __initconst = {
55 &clk[ipg],
56 &clk[uart1_gate],
57 &clk[uart2_gate],
58 &clk[uart3_gate],
59 &clk[uart4_gate],
60 &clk[uart5_gate],
[all …]
Dclk-imx35.c7 #include <linux/clk.h>
16 #include "clk.h"
83 static struct clk *clk[clk_max]; variable
85 static struct clk ** const uart_clks[] __initconst = {
86 &clk[ipg],
87 &clk[uart1_gate],
88 &clk[uart2_gate],
89 &clk[uart3_gate],
107 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); in _mx35_clocks_init()
115 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
[all …]
Dclk-imx21.c8 #include <linux/clk-provider.h>
17 #include "clk.h"
39 static struct clk *clk[IMX21_CLK_MAX]; variable
46 clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx21_clocks_init()
47 clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); in _mx21_clocks_init()
48 clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); in _mx21_clocks_init()
49 clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); in _mx21_clocks_init()
50 clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx21_clocks_init()
52 clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); in _mx21_clocks_init()
53 clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in _mx21_clocks_init()
[all …]
/Linux-v5.4/drivers/sh/clk/
Dcpg.c11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
[all …]
Dcore.c29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
[all …]
/Linux-v5.4/drivers/clk/mmp/
Dclk-mmp2.c12 #include <linux/clk.h>
19 #include <linux/clk/mmp.h>
21 #include "clk.h"
79 struct clk *clk; in mmp2_clk_init() local
80 struct clk *vctcxo; in mmp2_clk_init()
103 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in mmp2_clk_init()
104 clk_register_clkdev(clk, "clk32", NULL); in mmp2_clk_init()
109 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 800000000); in mmp2_clk_init()
110 clk_register_clkdev(clk, "pll1", NULL); in mmp2_clk_init()
112 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, 0, 480000000); in mmp2_clk_init()
[all …]
Dclk-pxa168.c12 #include <linux/clk.h>
20 #include "clk.h"
71 struct clk *clk; in pxa168_clk_init() local
72 struct clk *uart_pll; in pxa168_clk_init()
95 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in pxa168_clk_init()
96 clk_register_clkdev(clk, "clk32", NULL); in pxa168_clk_init()
98 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); in pxa168_clk_init()
99 clk_register_clkdev(clk, "vctcxo", NULL); in pxa168_clk_init()
101 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa168_clk_init()
102 clk_register_clkdev(clk, "pll1", NULL); in pxa168_clk_init()
[all …]
Dclk-pxa910.c12 #include <linux/clk.h>
20 #include "clk.h"
69 struct clk *clk; in pxa910_clk_init() local
70 struct clk *uart_pll; in pxa910_clk_init()
100 clk = clk_register_fixed_rate(NULL, "clk32", NULL, 0, 3200); in pxa910_clk_init()
101 clk_register_clkdev(clk, "clk32", NULL); in pxa910_clk_init()
103 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, 0, 26000000); in pxa910_clk_init()
104 clk_register_clkdev(clk, "vctcxo", NULL); in pxa910_clk_init()
106 clk = clk_register_fixed_rate(NULL, "pll1", NULL, 0, 624000000); in pxa910_clk_init()
107 clk_register_clkdev(clk, "pll1", NULL); in pxa910_clk_init()
[all …]
/Linux-v5.4/arch/arm/mach-omap1/
Dclock.c17 #include <linux/clk.h>
31 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
41 unsigned long omap1_uart_recalc(struct clk *clk) in omap1_uart_recalc() argument
43 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
44 return val & clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
47 unsigned long omap1_sossi_recalc(struct clk *clk) in omap1_sossi_recalc() argument
54 return clk->parent->rate / div; in omap1_sossi_recalc()
57 static void omap1_clk_allow_idle(struct clk *clk) in omap1_clk_allow_idle() argument
59 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; in omap1_clk_allow_idle()
61 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_allow_idle()
[all …]
Dclock.h13 #include <linux/clk.h>
19 struct clk;
26 #define CLK(dev, con, ck, cp) \ macro
32 .clk = ck, \
45 #define __clk_get_name(clk) (clk->name) argument
46 #define __clk_get_parent(clk) (clk->parent) argument
47 #define __clk_get_rate(clk) (clk->rate) argument
54 * @find_companion: function returning the "companion" clk reg for the clock
58 * A "companion" clk is an accompanying clock to the one being queried
68 int (*enable)(struct clk *);
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dstih418-clock.dtsi10 clk_sysin: clk-sysin {
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
28 compatible = "st,stih418-clk", "simple-bus";
50 clk_m_a9: clk-m-a9@92b0000 {
63 arm_periph_clk: clk-m-a9-periphs {
76 clk_s_a0_pll: clk-s-a0-pll {
82 clock-output-names = "clk-s-a0-pll-ofd-0";
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
93 clock-output-names = "clk-ic-lmi0",
94 "clk-ic-lmi1";
[all …]
Dstih410-clock.dtsi10 clk_sysin: clk-sysin {
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
28 compatible = "st,stih410-clk", "simple-bus";
50 clk_m_a9: clk-m-a9@92b0000 {
62 arm_periph_clk: clk-m-a9-periphs {
75 clk_s_a0_pll: clk-s-a0-pll {
81 clock-output-names = "clk-s-a0-pll-ofd-0";
82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
93 clock-output-names = "clk-ic-lmi0",
[all …]
Dstih407-clock.dtsi10 clk_sysin: clk-sysin {
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
47 clk_m_a9: clk-m-a9@92b0000 {
61 arm_periph_clk: clk-m-a9-periphs {
75 clk_s_a0_pll: clk-s-a0-pll {
81 clock-output-names = "clk-s-a0-pll-ofd-0";
82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
93 clock-output-names = "clk-ic-lmi0";
98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
[all …]
/Linux-v5.4/drivers/clk/spear/
Dspear3xx_clock.c12 #include <linux/clk.h>
18 #include "clk.h"
32 /* CORE CLK CFG register masks */
143 struct clk *clk; in spear300_clk_init() local
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
147 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
151 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
155 clk_register_clkdev(clk, NULL, "70000000.sdhci"); in spear300_clk_init()
[all …]
/Linux-v5.4/arch/mips/lantiq/
Dclk.c12 #include <linux/clk.h>
23 #include "clk.h"
27 static struct clk cpu_clk_generic[4];
38 struct clk *clk_get_cpu(void) in clk_get_cpu()
43 struct clk *clk_get_fpi(void) in clk_get_fpi()
49 struct clk *clk_get_io(void) in clk_get_io()
54 struct clk *clk_get_ppe(void) in clk_get_ppe()
60 static inline int clk_good(struct clk *clk) in clk_good() argument
62 return clk && !IS_ERR(clk); in clk_good()
65 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
[all …]
/Linux-v5.4/drivers/clk/mediatek/
DMakefile2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
4 obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
5 obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
6 obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
7 obj-$(CONFIG_COMMON_CLK_MT6779_IPESYS) += clk-mt6779-ipe.o
8 obj-$(CONFIG_COMMON_CLK_MT6779_CAMSYS) += clk-mt6779-cam.o
9 obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
10 obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
11 obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
12 obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
[all …]
/Linux-v5.4/arch/m68k/coldfire/
Dclk.c5 * clk.c -- general ColdFire CPU kernel clk handling
16 #include <linux/clk.h>
31 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
33 clk->enabled = 1; in __clk_init_enabled()
34 clk->clk_ops->enable(clk); in __clk_init_enabled()
37 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
39 clk->enabled = 0; in __clk_init_disabled()
40 clk->clk_ops->disable(clk); in __clk_init_disabled()
43 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
45 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0()
[all …]
/Linux-v5.4/drivers/clk/zte/
Dclk-zx296702.c7 #include <linux/clk-provider.h>
10 #include "clk.h"
18 static struct clk *topclk[ZX296702_TOPCLK_END];
19 static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
20 static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
196 static inline struct clk *zx_divtbl(const char *name, const char *parent, in zx_divtbl()
204 static inline struct clk *zx_div(const char *name, const char *parent, in zx_div()
211 static inline struct clk *zx_mux(const char *name, const char * const *parents, in zx_mux()
218 static inline struct clk *zx_gate(const char *name, const char *parent, in zx_gate()
227 struct clk **clk = topclk; in zx296702_top_clocks_init() local
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dsunxi.txt9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13 "allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
14 "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
15 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
16 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
17 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
18 "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
[all …]

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