| /Linux-v6.1/drivers/pwm/ |
| D | pwm-jz4740.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
11 #include <linux/clk.h>
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
40 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
41 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2); in jz4740_pwm_can_use_chn()
43 device_property_read_u32(jz->chip.dev->parent, in jz4740_pwm_can_use_chn()
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| D | pwm-spear.c | 12 #include <linux/clk.h>
21 #include <linux/pwm.h>
27 /* PWM registers and bits definitions */
47 * struct spear_pwm_chip - struct representing pwm chip
49 * @mmio_base: base address of pwm chip
50 * @clk: pointer to clk structure of pwm chip
51 * @chip: linux pwm chip representation
55 struct clk *clk; member
67 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
74 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
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| D | pwm-fsl-ftm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale FlexTimer Module (FTM) PWM Driver
5 * Copyright 2012-2013 Freescale Semiconductor, Inc.
8 #include <linux/clk.h>
18 #include <linux/pwm.h>
48 /* This value is valid iff a pwm is running */
51 struct clk *ipg_clk;
52 struct clk *clk[FSL_PWM_CLK_MAX]; member
66 regmap_read(fpc->regmap, FTM_FMS, &val); in ftm_clear_write_protection()
68 regmap_update_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS, in ftm_clear_write_protection()
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| D | pwm-vt8500.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-vt8500.c
15 #include <linux/pwm.h>
17 #include <linux/clk.h>
31 #define REG_CTRL(pwm) (((pwm) << 4) + 0x00) argument
32 #define REG_SCALAR(pwm) (((pwm) << 4) + 0x04) argument
33 #define REG_PERIOD(pwm) (((pwm) << 4) + 0x08) argument
34 #define REG_DUTY(pwm) (((pwm) << 4) + 0x0C) argument
53 struct clk *clk; member
64 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) in vt8500_pwm_busy_wait()
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| D | pwm-sunplus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PWM device driver for SUNPLUS SP7021 SoC
7 * https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
9 * Reference Manual(PWM module):
10 * https://sunplus.atlassian.net/wiki/spaces/doc/pages/461144198/12.+Pulse+Width+Modulation+PWM
13 * - Only supports normal polarity.
14 * - It output low when PWM channel disabled.
15 * - When the parameters change, current running period will not be completed
17 * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
23 #include <linux/clk.h>
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| D | pwm-clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Clock based PWM controller
7 * This is an "adapter" driver that allows PWM consumers to use
8 * system clocks with duty cycle control as PWM outputs.
11 * - Due to the fact that exact behavior depends on the underlying
13 * - Underlying clock may not be able to give 0% or 100% duty cycle
15 * - When the PWM is disabled, the clock will be disabled as well,
17 * - The clk API doesn't expose the necessary calls to implement
27 #include <linux/clk.h>
28 #include <linux/pwm.h>
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| D | pwm-ep93xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM framework driver for Cirrus Logic EP93xx
9 * platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
12 * platform device ep93xx-pwm.0 - PWMOUT
15 * platform device ep93xx-pwm.0 - PWMOUT
16 * platform device ep93xx-pwm.1 - PWMOUT1 (EGPIO14)
22 #include <linux/clk.h>
25 #include <linux/pwm.h>
38 struct clk *clk; member
47 static int ep93xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in ep93xx_pwm_request() argument
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| D | pwm-hibvt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM Controller Driver for HiSilicon BVT SoCs
9 #include <linux/clk.h>
15 #include <linux/pwm.h>
37 struct clk *clk; member
83 static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_enable() argument
87 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
91 static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_disable() argument
95 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
99 static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in hibvt_pwm_config() argument
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| D | pwm-pxa.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/pwm/pwm-pxa.c
5 * simple driver for PWM (Pulse Width Modulator) controller
7 * 2008-02-13 initial version
16 #include <linux/clk.h>
18 #include <linux/pwm.h>
26 /* PWM has_secondary_pwm? */
27 { "pxa25x-pwm", 0 },
28 { "pxa27x-pwm", HAS_SECONDARY_PWM },
29 { "pxa168-pwm", 0 },
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| D | pwm-sifive.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
14 #include <linux/clk.h>
18 #include <linux/pwm.h>
46 struct clk *clk; member
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| D | pwm-lpc32xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk.h>
14 #include <linux/pwm.h>
19 struct clk *clk; member
29 static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in lpc32xx_pwm_config() argument
36 c = clk_get_rate(lpc32xx->clk); in lpc32xx_pwm_config()
42 return -ERANGE; in lpc32xx_pwm_config()
47 duty_cycles = div64_u64((unsigned long long)(period_ns - duty_ns) * 256, in lpc32xx_pwm_config()
54 val = readl(lpc32xx->base + (pwm->hwpwm << 2)); in lpc32xx_pwm_config()
57 writel(val, lpc32xx->base + (pwm->hwpwm << 2)); in lpc32xx_pwm_config()
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| D | pwm-rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
9 #include <linux/clk.h>
15 #include <linux/pwm.h>
34 struct clk *clk; member
35 struct clk *pclk;
61 struct pwm_device *pwm, in rockchip_pwm_get_state() argument
65 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
71 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
75 ret = clk_enable(pc->clk); in rockchip_pwm_get_state()
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| D | pwm-berlin.c | 2 * Marvell Berlin PWM driver
6 * Author: Antoine Tenart <antoine.tenart@free-electrons.com>
13 #include <linux/clk.h>
18 #include <linux/pwm.h>
50 struct clk *clk; member
62 return readl_relaxed(bpc->base + channel * 0x10 + offset); in berlin_pwm_readl()
69 writel_relaxed(value, bpc->base + channel * 0x10 + offset); in berlin_pwm_writel()
72 static int berlin_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in berlin_pwm_request() argument
78 return -ENOMEM; in berlin_pwm_request()
80 return pwm_set_chip_data(pwm, channel); in berlin_pwm_request()
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| D | pwm-keembay.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Keem Bay PWM driver
10 * - Upon disabling a channel, the currently running
17 #include <linux/clk.h>
22 #include <linux/pwm.h>
34 /* PWM Register offset */
41 struct clk *clk; member
55 static int keembay_clk_enable(struct device *dev, struct clk *clk) in keembay_clk_enable() argument
59 ret = clk_prepare_enable(clk); in keembay_clk_enable()
63 return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk); in keembay_clk_enable()
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| D | pwm-bcm-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk.h>
13 #include <linux/pwm.h>
18 * The Kona PWM has some unusual characteristics. Here are the main points.
34 * 5) When the external clock that feeds the PWM is disabled, output is pegged
61 struct clk *clk; member
75 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
79 writel(value, kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
83 * it. Failing to do this may result in no PWM signal. in kona_pwmc_prepare_for_settings()
90 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_apply_settings()
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| D | pwm-atmel-tcb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
21 #include <linux/pwm.h>
37 enum pwm_polarity polarity; /* PWM polarity */
38 unsigned div; /* PWM clock divider */
39 unsigned duty; /* PWM duty expressed in clk cycles */
40 unsigned period; /* PWM period expressed in clk cycles */
57 struct clk *clk; member
58 struct clk *gclk;
59 struct clk *slow_clk;
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| D | pwm-sun4i.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
13 #include <linux/clk.h>
22 #include <linux/pwm.h>
48 #define PWM_PRD(prd) (((prd) - 1) << 16)
86 struct clk *bus_clk;
87 struct clk *clk; member
102 return readl(chip->base + offset); in sun4i_pwm_readl()
108 writel(val, chip->base + offset); in sun4i_pwm_writel()
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| D | pwm-mxs.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk.h>
13 #include <linux/pwm.h>
41 struct clk *clk; member
47 static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in mxs_pwm_apply() argument
58 * If the PWM channel is disabled, make sure to turn on the in mxs_pwm_apply()
62 if (!pwm_is_enabled(pwm)) { in mxs_pwm_apply()
63 ret = clk_prepare_enable(mxs->clk); in mxs_pwm_apply()
68 if (!state->enabled && pwm_is_enabled(pwm)) in mxs_pwm_apply()
69 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); in mxs_pwm_apply()
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| D | pwm-bcm2835.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk.h>
12 #include <linux/pwm.h>
17 #define PWM_MODE 0x80 /* set timer in PWM mode */
30 struct clk *clk; member
38 static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in bcm2835_pwm_request() argument
43 value = readl(pc->base + PWM_CONTROL); in bcm2835_pwm_request()
44 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
46 writel(value, pc->base + PWM_CONTROL); in bcm2835_pwm_request()
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| D | pwm-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
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| D | pwm-atmel.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
22 #include <linux/clk.h>
30 #include <linux/pwm.h>
33 /* The following is global registers for PWM controller */
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| D | pwm-bcm-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk.h>
12 #include <linux/pwm.h>
29 #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
39 struct clk *clk; member
51 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
53 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
63 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
65 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
71 static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in iproc_pwmc_get_state() argument
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| D | pwm-meson.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * PWM controller driver for Amlogic Meson SoCs.
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
32 #include <linux/clk.h>
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| D | pwm-tiecap.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ECAP PWM driver
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
12 #include <linux/clk.h>
14 #include <linux/pwm.h>
50 static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in ecap_pwm_config() argument
58 c = pc->clk_rate; in ecap_pwm_config()
67 c = pc->clk_rate; in ecap_pwm_config()
73 pm_runtime_get_sync(pc->chip.dev); in ecap_pwm_config()
75 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
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| D | pwm-intel-lgm.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * - The hardware supports fixed period & configures only 2-wire mode.
7 * - Supports normal polarity. Does not support changing polarity.
8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
10 * - When duty cycle is changed, PWM output may be a mix of previous setting
13 * - It is a dedicated PWM fan controller. There are no other consumers for
14 * this PWM controller.
17 #include <linux/clk.h>
21 #include <linux/pwm.h>
36 #define LGM_PWM_MAX_RPM (BIT(16) - 1)
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