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/Linux-v5.10/Documentation/devicetree/bindings/mmc/
Dsdhci-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
26 - reg-names
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/Linux-v5.10/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
28 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
104 u32 clk; member
105 u32 t_bacc; /* burst access valid clock to output delay */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
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/Linux-v5.10/drivers/memory/
Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
13 #include <linux/clk.h>
53 struct clk *clk; member
61 int cycles; in pl172_timing_prop() local
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
66 if (cycles < 0) { in pl172_timing_prop()
67 cycles = 0; in pl172_timing_prop()
68 } else if (cycles > max) { in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
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/Linux-v5.10/drivers/watchdog/
Drenesas_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
9 #include <linux/clk.h>
10 #include <linux/delay.h>
36 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
38 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
39 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
62 writel_relaxed(val, priv->base + reg); in rwdt_write()
69 rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT); in rwdt_init_timeout()
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Dimgpdc_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * -----
12 * The timeout value is rounded to the next power of two clock cycles.
16 * timeout = 2^(delay + 1) clock cycles
18 * Where 'delay' is the value written in PDC_WDT_CONFIG register.
21 * as a power of two number of watchdog clock cycles. The current implementation
25 * The following table shows how the user-configured timeout relates
29 * -----------------------------------
40 #include <linux/clk.h>
84 struct clk *wdt_clk;
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Dcoh901327_wdt.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2008-2009 ST-Ericsson AB
6 * Watchdog driver for the ST-Ericsson AB COH 901 327 IP core
18 #include <linux/clk.h>
19 #include <linux/delay.h>
28 /* WDOG_FEED Register 32bit (-/W) */
34 /* WDOG_DISABLE1 Register 32bit (-/W) */
47 /* WDOG_COUNT Register 32bit (R/-) */
56 /* WDOG_RESTART Register 32bit (-/W) */
78 static struct clk *clk; variable
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/Linux-v5.10/drivers/cpufreq/
Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
19 #include <soc/tegra/bpmp-abi.h>
47 u32 delay; member
67 * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
87 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
97 * ref_clk_counter(32 bit counter) runs on constant clk, in tegra_read_counters()
99 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter in tegra_read_counters()
105 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter in tegra_read_counters()
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/Linux-v5.10/drivers/char/hw_random/
Dks-sa-rng.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com
16 #include <linux/clk.h>
23 #include <linux/delay.h>
64 /* Number of CLK input cycles between samples */
70 /* Delay between retries (in usecs) */
86 struct clk *clk; member
93 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) in cycles_to_ns() argument
96 cycles, clk_rate); in cycles_to_ns()
116 struct device *dev = (struct device *)rng->priv; in ks_sa_rng_init()
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/Linux-v5.10/drivers/pwm/
Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
22 #include <linux/clk.h>
23 #include <linux/delay.h>
83 struct clk *clk; member
100 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
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/Linux-v5.10/drivers/clk/mmp/
Dclk-gate.c12 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
18 #include "clk.h"
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
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/Linux-v5.10/drivers/iio/adc/
Dcc10001_adc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
6 #include <linux/clk.h>
7 #include <linux/delay.h>
48 * As per device specification, wait six clock cycles after power-up to
49 * activate START. Since adding two more clock cycles delay does not
50 * impact the performance too much, we are adding two additional cycles delay
57 struct clk *adc_clk;
70 writel(val, adc_dev->reg_base + reg); in cc10001_adc_write_reg()
76 return readl(adc_dev->reg_base + reg); in cc10001_adc_read_reg()
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/Linux-v5.10/arch/arm/boot/dts/
Dmmp2-olpc-xo-1-75.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/linux-event-codes.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
15 model = "OLPC XO-1.75";
16 compatible = "olpc,xo-1.75", "mrvl,mmp2";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 compatible = "simple-framebuffer";
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Dqcom-apq8060-dragonboard.dts23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
26 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
27 #include "qcom-msm8660.dtsi"
31 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
38 stdout-path = "serial0:115200n8";
42 compatible = "simple-bus";
45 vph: regulator-fixed {
46 compatible = "regulator-fixed";
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/Linux-v5.10/drivers/clocksource/
Dtimer-fttmr010.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
18 #include <linux/clk.h>
21 #include <linux/delay.h>
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
112 * A local singleton used by sched_clock and delay timer reads, which are
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
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Dtimer-imx-tpm.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk.h>
9 #include <linux/delay.h>
13 #include "timer-of.h"
95 * contention between GPU and A7 may results a few cycles delay in tpm_set_next_event()
99 return (int)(next - now) <= 0 ? -ETIME : 0; in tpm_set_next_event()
122 evt->event_handler(evt); in tpm_timer_interrupt()
159 "imx-tpm", in tpm_clocksource_init()
171 GENMASK(counter_width - 1, in tpm_clockevent_init()
177 struct clk *ipg; in tpm_timer_init()
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Dtimer-sun5i.c6 * Maxime Ripard <maxime.ripard@free-electrons.com>
13 #include <linux/clk.h>
16 #include <linux/delay.h>
43 struct clk *clk; member
68 * When we disable a timer, we need to wait at least for 2 cycles of
75 u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
77 while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
83 u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
84 writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
89 static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay) in sun5i_clkevt_time_setup() argument
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Dtimer-u300.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2009 ST-Ericsson AB
14 #include <linux/clk.h>
17 #include <linux/delay.h>
35 /* Reset OS Timer 32bit (-/W) */
38 /* Enable OS Timer 32bit (-/W) */
41 /* Disable OS Timer 32bit (-/W) */
44 /* OS Timer Mode Register 32bit (-/W) */
48 /* OS Timer Status Register 32bit (R/-) */
59 /* OS Timer Current Count Register 32bit (R/-) */
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Dexynos_mct.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/arch/arm/mach-exynos4/mct.c
7 * Exynos4 MCT(Multi-Core Timer) support
13 #include <linux/clk.h>
16 #include <linux/delay.h>
161 * exynos4_read_count_64 - Read all 64-bits of the global counter
163 * This will read all 64-bits of the global counter taking care to make sure
165 * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
168 * Returns the number of cycles in the global counter.
185 * exynos4_read_count_32 - Read the lower 32-bits of the global counter
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/Linux-v5.10/drivers/nvmem/
Dmxs-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
9 #include <linux/clk.h>
10 #include <linux/delay.h>
15 #include <linux/nvmem-provider.h>
31 struct clk *clk; member
41 while (timeout--) { in mxs_ocotp_wait()
42 status = readl(otp->base); in mxs_ocotp_wait()
51 return -EBUSY; in mxs_ocotp_wait()
53 return -EIO; in mxs_ocotp_wait()
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/Linux-v5.10/Documentation/devicetree/bindings/memory-controllers/
Domap-gpmc.txt7 - compatible: Should be set to one of the following:
9 ti,omap2420-gpmc (omap2420)
10 ti,omap2430-gpmc (omap2430)
11 ti,omap3430-gpmc (omap3430 & omap3630)
12 ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
13 ti,am3352-gpmc (am335x devices)
15 - reg: A resource specifier for the register space
17 - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
19 - #address-cells: Must be set to 2 to allow memory address translation
20 - #size-cells: Must be set to 1 to allow CS address passing
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/Linux-v5.10/drivers/mmc/host/
Dsdhci-pxav2.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/clk.h>
25 #include "sdhci-pltfm.h"
46 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); in pxav2_reset()
47 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; in pxav2_reset()
58 if (pdata && pdata->clk_delay_sel == 1) { in pxav2_reset()
59 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
62 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) in pxav2_reset()
67 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
70 if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) { in pxav2_reset()
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/Linux-v5.10/drivers/net/ethernet/ti/
Dam65-cpts.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
23 #include "am65-cpts.h"
164 struct clk *refclk;
186 #define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
187 #define am65_cpts_read32(c, r) readl(&(c)->reg->r)
204 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7; in am65_cpts_set_add_val()
206 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val); in am65_cpts_set_add_val()
[all …]
/Linux-v5.10/drivers/mtd/devices/
Dst_spi_fsm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller
7 * Copyright (C) 2010-2014 STMicroelectronics Limited
18 #include <linux/mtd/spi-nor.h>
20 #include <linux/delay.h>
23 #include <linux/clk.h>
261 struct clk *clk; member
282 uint8_t mode_cycles; /* No. of MODE cycles */
283 uint8_t dummy_cycles; /* No. of DUMMY cycles */
318 * ST Microelectronics/Numonyx --
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/Linux-v5.10/drivers/spi/
Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
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/Linux-v5.10/drivers/regulator/
Dti-abb-regulator.c7 * Copyright (C) 2012-2013 Texas Instruments, Inc.
20 #include <linux/clk.h>
21 #include <linux/delay.h>
35 * FAST_OPP: sets ABB LDO to Forward Body-Bias
36 * SLOW_OPP: sets ABB LDO to Reverse Body-Bias
43 * struct ti_abb_info - ABB information per voltage setting
56 * struct ti_abb_reg - Register description for ABB block
59 * @sr2_wtcnt_value_mask: setup register- sr2_wtcnt_value mask
60 * @fbb_sel_mask: setup register- FBB sel mask
61 * @rbb_sel_mask: setup register- RBB sel mask
[all …]

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