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/Linux-v5.15/Documentation/devicetree/bindings/mmc/
Drockchip-dw-mshc.yaml54 Handle to "biu" and "ciu" clocks for the bus interface unit clock and
55 the card interface unit clock. If "ciu-drive" and "ciu-sample" are
63 - const: ciu
64 - const: ciu-drive
65 - const: ciu-sample
67 Apart from the clock-names "biu" and "ciu" two more clocks
68 "ciu-drive" and "ciu-sample" are supported. They are used
69 to control the clock phases, "ciu-sample" is required for tuning
78 The default phase to set "ciu-sample" at probing,
112 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Dhi3798cv200-dw-mshc.txt17 "ciu" - The ciu clock described in synopsys-dw-mshc.txt.
19 "ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
20 "ciu-drive" - Hi3798CV200 extended phase clock for ciu driving.
32 clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
Dexynos-dw-mshc.txt26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
27 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
48 Valid values for SDR and DDR CIU clock timing for Exynos5250:
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
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Dsynopsys-dw-mshc.yaml30 Handle to "biu" and "ciu" clocks for the
36 - const: ciu
54 clock-names = "biu", "ciu";
Dsynopsys-dw-mshc-common.yaml25 Should be the frequency (in Hz) of the ciu clock. If this
26 is specified and the ciu clock is specified then we'll try to set the ciu
Dk3-dw-mshc.txt36 clock-names = "ciu", "biu";
66 clock-names = "ciu", "biu";
Dimg-dw-mshc.txt23 clock-names = "biu", "ciu";
/Linux-v5.15/Documentation/devicetree/bindings/mips/cavium/
Dciu.txt4 - compatible: "cavium,octeon-3860-ciu"
10 - reg: The base address of the CIU's register bank.
13 the CIU and may have a value of 0 or 1. The second cell is the bit
18 compatible = "cavium,octeon-3860-ciu";
Dciu2.txt10 - reg: The base address of the CIU's register bank.
13 the CIU and may have a value between 0 and 63. The second cell is
Dcib.txt16 - interrupts: The CIU line to which the CIB block is connected.
31 interrupt-parent = <&ciu>;
Dciu3.txt10 - reg: The base address of the CIU's register bank.
/Linux-v5.15/drivers/mmc/host/
Ddw_mmc-hi3798cv200.c136 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); in dw_mci_hi3798cv200_init()
138 dev_err(host->dev, "failed to get ciu-sample clock\n"); in dw_mci_hi3798cv200_init()
142 priv->drive_clk = devm_clk_get(host->dev, "ciu-drive"); in dw_mci_hi3798cv200_init()
144 dev_err(host->dev, "failed to get ciu-drive clock\n"); in dw_mci_hi3798cv200_init()
150 dev_err(host->dev, "failed to enable ciu-sample clock\n"); in dw_mci_hi3798cv200_init()
156 dev_err(host->dev, "failed to enable ciu-drive clock\n"); in dw_mci_hi3798cv200_init()
Ddw_mmc-rockchip.c278 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive"); in dw_mci_rk3288_parse_dt()
280 dev_dbg(host->dev, "ciu-drive not available\n"); in dw_mci_rk3288_parse_dt()
282 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample"); in dw_mci_rk3288_parse_dt()
284 dev_dbg(host->dev, "ciu-sample not available\n"); in dw_mci_rk3288_parse_dt()
/Linux-v5.15/arch/mips/cavium-octeon/
Docteon-irq.c76 struct { /* only used for ciu/ciu2 */
83 int ciu_node; /* NUMA node number of the CIU */
794 * For non-v2 CIU, we will allow only single CPU affinity. in octeon_irq_ciu_set_affinity()
927 * Newer octeon chips have support for lockless CIU operation.
930 .name = "CIU",
942 .name = "CIU",
955 * Newer octeon chips have support for lockless CIU operation.
958 .name = "CIU",
970 .name = "CIU",
983 .name = "CIU",
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DKconfig71 tristate "Module to measure interrupt latency using Octeon CIU Timer"
74 the CIU Timers on Octeon.
/Linux-v5.15/arch/arm64/boot/dts/rockchip/
Drk3568.dtsi266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
280 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Drk3368.dtsi184 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
198 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
212 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
/Linux-v5.15/Documentation/devicetree/bindings/clock/
Daltr_socfpga.txt27 the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
29 hold/delay times that is needed for the SD/MMC CIU clock. The values of both
/Linux-v5.15/arch/arm/boot/dts/
Dexynos5260-xyref5260.dts71 samsung,dw-mshc-ciu-div = <3>;
83 samsung,dw-mshc-ciu-div = <3>;
Drv1108.dtsi481 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
493 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
505 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Dexynos5410-smdk5410.dts51 samsung,dw-mshc-ciu-div = <3>;
61 samsung,dw-mshc-ciu-div = <3>;
Drk3036.dtsi254 clock-names = "biu", "ciu";
268 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
286 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
Drk322x.dtsi750 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
763 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
778 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
/Linux-v5.15/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dtsi10 interrupt-parent = <&ciu>;
18 ciu: interrupt-controller@1070000000000 { label
19 compatible = "cavium,octeon-3860-ciu";
/Linux-v5.15/arch/arc/boot/dts/
Dhsdk.dts154 mmcclk_ciu: mmcclk-ciu {
157 * DW sdio controller has external ciu clock divider
260 clock-names = "biu", "ciu";

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