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Searched +full:ce4100 +full:- +full:ioapic (Results 1 – 6 of 6) sorted by relevance

/Linux-v6.6/Documentation/devicetree/bindings/interrupt-controller/
Dintel,ce4100-ioapic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
18 from internal sources and from an external I/O APIC (ioapic).
22 Many of the Intel's generic devices like hpet, ioapic, lapic have
23 the ce4100 name in their compatible property names because they
24 first appeared in CE4100 SoC.
28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
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Dintel,ce4100-lapic.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
18 from internal sources and from an external I/O APIC (ioapic).
22 Many of the Intel's generic devices like hpet, ioapic, lapic have
23 the ce4100 name in their compatible property names because they
24 first appeared in CE4100 SoC.
28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf
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/Linux-v6.6/arch/x86/platform/ce4100/
Dfalconfalls.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * CE4100 on Falcon Falls
7 /dts-v1/;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "intel,ce4100";
27 #address-cells = <1>;
28 #size-cells = <1>;
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Dce4100.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel CE4100 platform specific setup code
14 #include <asm/ce4100.h>
20 #include <asm/emergency-restart.h>
23 * The CE4100 platform has an internal 8051 Microcontroller which is
38 offset = offset << p->regshift; in mem_serial_in()
39 return readl(p->membase + offset); in mem_serial_in()
49 * errata number 9 in Errata - B step.
57 offset = offset << p->regshift; in ce4100_mem_serial_in()
58 ret = readl(p->membase + offset); in ce4100_mem_serial_in()
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/Linux-v6.6/arch/x86/kernel/
Ddevicetree.c1 // SPDX-License-Identifier: GPL-2.0
40 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
43 { .compatible = "intel,ce4100-cp", },
67 prop = of_get_property(np, "bus-range", NULL); in pcibios_get_phb_of_node()
71 if (bus->number == bus_min) in pcibios_get_phb_of_node()
91 return -EINVAL; in x86_of_pci_irq_enable()
92 dev->irq = virq; in x86_of_pci_irq_enable()
114 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet"); in dtb_setup_hpet()
150 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic"); in dtb_lapic_setup()
167 pic_mode = !of_property_read_bool(dn, "intel,virtual-wire-mode"); in dtb_lapic_setup()
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/Linux-v6.6/arch/x86/kernel/apic/
Dvector.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
78 info->mask = mask; in init_irq_alloc_info()
94 while (irqd->parent_data) in apic_chip_data()
95 irqd = irqd->parent_data; in apic_chip_data()
97 return irqd->chip_data; in apic_chip_data()
104 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
119 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
135 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
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