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/Linux-v5.10/drivers/pinctrl/
Dpinctrl-ingenic.c861 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a),
862 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b),
863 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d),
864 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e),
880 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b),
881 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d),
882 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e),
943 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
951 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1169 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23),
[all …]
Dpinctrl-gemini.c610 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
632 /* Serial flash pins CE0, CE1, DI, DO, CK */
653 /* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */
656 /* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */
659 /* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */
1559 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */
1581 /* Serial flash pins CE0, CE1, DI, DO, CK */
1599 /* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */
1605 /* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */
/Linux-v5.10/Documentation/devicetree/bindings/net/wireless/
Dqcom,ath11k.yaml33 - description: interrupt event for ring CE0
89 - const: ce0
226 "ce0",
/Linux-v5.10/Documentation/devicetree/bindings/media/spi/
Dsony-cxd2880.txt16 reg = <0>; /* CE0 */
/Linux-v5.10/drivers/mtd/spi-nor/controllers/
Daspeed-smc.c38 u8 we0; /* shift for write enable bit for CE0 */
39 u8 ctl0; /* offset in regs of ctl for CE0 */
119 * CE0 and CE1 can only be of type SPI. CE2 can be of type NOR but the
546 * The AST2500 SPI controller has a HW bug when the CE0 chip in aspeed_smc_chip_set_segment()
563 * start address if we are handling CE0 or use the previous in aspeed_smc_chip_set_segment()
637 * register. It uses the CE0 control register to set 4Byte mode at the
/Linux-v5.10/arch/arm/boot/dts/
Dgemini-rut1xx.dts52 /* Conflict with NAND CE0 */
Dgemini-sl93512r.dts64 /* Conflict with NAND flash CE0 (no problem) */
Dsun7i-a20-bananapi.dts247 "", "", "SPI-CE0", "SPI-CLK", "SPI-MOSI",
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/top/
Dgk104.c79 case 0x00000001: A_(CE0 ); break; in gk104_top_oneinit()
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/core/
Dsubdev.c59 [NVKM_ENGINE_CE0 ] = "ce0",
/Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgv100.c168 { 0x01, "CE0" },
Dgk104.c1087 { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 },
1120 { 0x01, "CE0" },
/Linux-v5.10/drivers/net/wireless/ath/ath11k/
Dhw.c285 /* CE0: host->target HTC control and raw streams */
618 /* CE0: host->target HTC control and raw streams */
Dce.c11 /* CE0: host->target HTC control and raw streams */
113 /* CE0: host->target HTC control and raw streams */
Dahb.c45 "ce0",
/Linux-v5.10/drivers/crypto/nx/
Dnx-842-pseries.c80 * CE0 0=full completion, 1=partial completion
81 * CE1 0=CE0 indicates completion, 1=termination (output may be modified)
/Linux-v5.10/drivers/pinctrl/sunxi/
Dpinctrl-sun6i-a31.c322 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
847 SUNXI_FUNCTION(0x2, "nand1")), /* CE0 */
Dpinctrl-sun8i-a33.c95 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
Dpinctrl-sun8i-h3.c173 SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
/Linux-v5.10/drivers/net/wireless/ath/ath10k/
Dsnoc.c135 /* CE0: host->target HTC control streams */
242 /* CE0: host->target HTC control and raw streams */
/Linux-v5.10/sound/pci/asihpi/
Dhpi6205.c1610 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */ in boot_loader_config_emif()
1624 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */ in boot_loader_config_emif()
1763 /* EMIF CE0 setup - 2Mx32 Sync DRAM in boot_loader_config_emif()
Dhpi6000.c797 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz in hpi6000_adapter_boot_load_dsp()
819 /* EMIF CE0 setup - 2Mx32 Sync DRAM in hpi6000_adapter_boot_load_dsp()
/Linux-v5.10/drivers/interconnect/qcom/
Dsc7180.c162 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
Dsdm845.c161 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
Dsm8150.c172 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);

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