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/Linux-v6.1/arch/riscv/mm/
Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * Performs an icache flush for the given MM context. RISC-V has no direct
34 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
47 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
60 if (mm == current->active_mm && local) { in flush_icache_mm()
86 if (!test_and_set_bit(PG_dcache_clean, &page->flags)) in flush_icache_pte()
109 /* set block-size for cbom extension if available */ in riscv_init_cbom_blocksize()
110 ret = of_property_read_u32(node, "riscv,cbom-block-size", &val); in riscv_init_cbom_blocksize()
119 pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", in riscv_init_cbom_blocksize()
Ddma-noncoherent.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
15 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, in arch_sync_dma_for_device() argument
22 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); in arch_sync_dma_for_device()
25 ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); in arch_sync_dma_for_device()
28 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); in arch_sync_dma_for_device()
35 void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, in arch_sync_dma_for_cpu() argument
45 ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); in arch_sync_dma_for_cpu()
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/Linux-v6.1/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
29 - items:
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