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/Linux-v6.6/Documentation/devicetree/bindings/mmc/
Darm,pl18x.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
15 reading and writing to MultiMedia and SD cards alike. Over the years
16 vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
29 - arm,pl180
[all …]
Dingenic,mmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: mmc-controller.yaml#
18 - enum:
19 - ingenic,jz4740-mmc
20 - ingenic,jz4725b-mmc
21 - ingenic,jz4760-mmc
22 - ingenic,jz4775-mmc
[all …]
Dk3-dw-mshc.txt4 Read synopsys-dw-mshc.txt for more details
7 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
22 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
30 compatible = "hisilicon,hi4511-dw-mshc";
33 #address-cells = <1>;
[all …]
Dcavium-mmc.txt3 The highspeed MMC host controller on Caviums SoCs provides an interface
4 for MMC and SD types of memory cards.
7 as the speed of SD standard 4.0. Only 3.3 Volt is supported.
10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
[all …]
/Linux-v6.6/arch/arm/boot/dts/rockchip/
Drockchip-radxa-dalang-carrier.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/pwm/pwm.h>
11 clkin_gmac: external-gmac-clock {
12 compatible = "fixed-clock";
13 clock-frequency = <125000000>;
14 clock-output-names = "clkin_gmac";
15 #clock-cells = <0>;
18 sdio_pwrseq: sdio-pwrseq {
19 compatible = "mmc-pwrseq-simple";
21 clock-names = "ext_clock";
[all …]
Drk3288-veyron-sdmmc.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
15 sdcard-supply = <&vccio_sd>;
24 sdmmc_bus4: sdmmc-bus4 {
31 sdmmc_clk: sdmmc-clk {
35 sdmmc_cmd: sdmmc-cmd {
45 sdmmc_cd_disabled: sdmmc-cd-disabled {
50 sdmmc_cd_pin: sdmmc-cd-pin {
57 vcc9-supply = <&vcc_5v>;
61 regulator-name = "vccio_sd";
62 regulator-min-microvolt = <1800000>;
[all …]
Drv1126-edgeble-neu2-io.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "rv1126-edgeble-neu2.dtsi"
13 compatible = "edgeble,neural-compute-module-2-io",
14 "edgeble,neural-compute-module-2", "rockchip,rv1126";
21 stdout-path = "serial2:1500000n8";
24 vcc12v_dcin: vcc12v-dcin-regulator {
25 compatible = "regulator-fixed";
26 regulator-name = "vcc12v_dcin";
27 regulator-always-on;
[all …]
/Linux-v6.6/arch/riscv/boot/dts/microchip/
Dmpfs-polarberry.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
4 /dts-v1/;
7 #include "mpfs-polarberry-fabric.dtsi"
22 stdout-path = "serial0:115200n8";
26 timebase-frequency = <MTIMER_FREQ>;
45 phy-mode = "sgmii";
46 phy-handle = <&phy0>;
51 phy-mode = "sgmii";
52 phy-handle = <&phy1>;
[all …]
Dmpfs-sev-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
7 #include "mpfs-sev-kit-fabric.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
15 model = "Microchip PolarFire-SoC SEV Kit";
16 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
28 stdout-path = "serial1:115200n8";
32 timebase-frequency = <MTIMER_FREQ>;
35 reserved-memory {
[all …]
Dmpfs-m100pfsevp.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
8 /dts-v1/;
11 #include "mpfs-m100pfs-fabric.dtsi"
33 stdout-path = "serial1:115200n8";
37 timebase-frequency = <MTIMER_FREQ>;
70 pmic-irq-hog {
71 gpio-hog;
[all …]
/Linux-v6.6/arch/arm/boot/dts/st/
Dste-href.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/leds/common.h>
8 #include "ste-href-family-pinctrl.dtsi"
17 compatible = "simple-battery";
18 battery-type = "lithium-ion-polymer";
21 thermal-zones {
22 battery-thermal {
24 polling-delay = <0>;
[all …]
/Linux-v6.6/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10_socdk_sdmmc.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
6 /dts-v1/;
11 cap-sd-highspeed;
12 cap-mmc-highspeed;
13 broken-cd;
14 bus-width = <4>;
15 clk-phase-sd-hs = <0>, <135>;
19 sdmmca-ecc@ff8c2c00 {
20 compatible = "altr,socfpga-sdmmc-ecc";
[all …]
Dsocfpga_arria5.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
Dsocfpga_cyclone5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
/Linux-v6.6/arch/arm64/boot/dts/rockchip/
Drk3308-roc-cc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 model = "Firefly ROC-RK3308-CC board";
11 compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
19 stdout-path = "serial2:1500000n8";
22 ir-receiver {
23 compatible = "gpio-ir-receiver";
25 pinctrl-names = "default";
26 pinctrl-0 = <&ir_recv_pin>;
30 compatible = "pwm-ir-tx";
[all …]
Dpx30-engicam-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 vcc5v0_sys: vcc5v0-sys {
15 compatible = "regulator-fixed";
16 regulator-name = "vcc5v0_sys"; /* +5V */
17 regulator-always-on;
18 regulator-boot-on;
19 regulator-min-microvolt = <5000000>;
20 regulator-max-microvolt = <5000000>;
23 sdio_pwrseq: sdio-pwrseq {
24 compatible = "mmc-pwrseq-simple";
[all …]
Drk3308-rock-pi-s.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
21 stdout-path = "serial0:1500000n8";
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
27 pinctrl-0 = <&green_led_gio>, <&heartbeat_led_gpio>;
29 green-led {
30 default-state = "on";
33 linux,default-trigger = "default-on";
36 blue-led {
[all …]
Drk3588-edgeble-neu6b-io.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "rk3588-edgeble-neu6b.dtsi"
12 compatible = "edgeble,neural-compute-module-6b-io",
13 "edgeble,neural-compute-module-6b", "rockchip,rk3588";
20 stdout-path = "serial2:1500000n8";
34 interrupt-parent = <&gpio0>;
36 #clock-cells = <0>;
37 clock-output-names = "hym8563";
38 pinctrl-names = "default";
[all …]
Drk3568-fastrhino-r66s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "rk3568-fastrhino-r66s.dtsi"
7 compatible = "lunzn,fastrhino-r66s", "rockchip,rk3568";
15 bus-width = <4>;
16 cap-mmc-highspeed;
17 cap-sd-highspeed;
18 disable-wp;
19 max-frequency = <150000000>;
20 no-sdio;
21 no-mmc;
[all …]
/Linux-v6.6/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb-p20x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "meson-gxbb.dtsi"
17 stdout-path = "serial0:115200n8";
25 usb_pwr: regulator-usb-pwrs {
26 compatible = "regulator-fixed";
28 regulator-name = "USB_PWR";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
35 enable-active-high;
38 vddio_card: gpio-regulator {
[all …]
Dmeson-gxl-s905x-p212.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on meson-gx-p23x-q20x.dtsi:
5 * - Copyright (c) 2016 Endless Computers, Inc.
7 * - Copyright (c) 2016 BayLibre, SAS.
13 #include "meson-gxl-s905x.dtsi"
22 stdout-path = "serial0:115200n8";
30 hdmi_5v: regulator-hdmi-5v {
31 compatible = "regulator-fixed";
33 regulator-name = "HDMI_5V";
34 regulator-min-microvolt = <5000000>;
[all …]
Dmeson-gxl-s905x-nexbox-a95x.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxl-s905x.dtsi"
13 compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl";
22 stdout-path = "serial0:115200n8";
30 vddio_card: gpio-regulator {
31 compatible = "regulator-gpio";
33 regulator-name = "VDDIO_CARD";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
[all …]
/Linux-v6.6/arch/arm/boot/dts/qcom/
Dqcom-msm8660.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
[all …]
/Linux-v6.6/arch/arm/boot/dts/amlogic/
Dmeson8m2-mxiii-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Oleg Ivanov <balbes-150@yandex.ru>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "tronsmart,mxiii-plus", "amlogic,meson8m2";
26 stdout-path = "serial0:115200n8";
34 adc-keys {
35 compatible = "adc-keys";
36 io-channels = <&saradc 0>;
[all …]
/Linux-v6.6/arch/mips/boot/dts/ingenic/
Djz4770.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
6 #address-cells = <1>;
7 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
16 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
20 clock-names = "cpu";
24 cpuintc: interrupt-controller {
[all …]

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