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/Linux-v6.6/Documentation/devicetree/bindings/net/can/
Drenesas,rcar-canfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN FD Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
15 - items:
16 - enum:
17 - renesas,r8a774a1-canfd # RZ/G2M
18 - renesas,r8a774b1-canfd # RZ/G2N
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Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
22 maxItems: 1
25 maxItems: 1
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Drenesas,rcar-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN Controller
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
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Dctu,ctucanfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CTU CAN FD Open-source IP Core
10 Open-source CAN FD IP core developed at the Czech Technical University in Prague
13 [1] sources : https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
21 …tps://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-ca…
24 - Pavel Pisa <pisa@cmp.felk.cvut.cz>
25 - Ondrej Ille <ondrej.ille@gmail.com>
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/Linux-v6.6/drivers/net/can/ifi_canfd/
Difi_canfd.c2 * CAN bus driver for IFI CANFD controller
7 * http://www.ifi-pld.de/IP/CANFD/canfd.html
49 #define IFI_CANFD_TXSTCMD_HIGH_PRIO BIT(1)
57 #define IFI_CANFD_INTERRUPT_ERROR_WARNING BIT(1)
69 #define IFI_CANFD_IRQMASK_ERROR_WARNING BIT(1)
122 #define IFI_CANFD_ERROR_CTR_ACK_ERROR_FIRST BIT(1)
218 /* IFI CANFD private data structure */
237 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) in ifi_canfd_irq_enable()
245 priv->base + IFI_CANFD_IRQMASK); in ifi_canfd_irq_enable()
250 struct net_device_stats *stats = &ndev->stats; in ifi_canfd_read_fifo()
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/Linux-v6.6/arch/arm64/boot/dts/renesas/
Drzg2lc-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 #include "rzg2lc-smarc-pinfunction.dtsi"
12 #include "rz-smarc-common.dtsi"
20 osc1: cec-clock {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <12000000>;
26 hdmi-out {
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Drzg2ul-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts
8 #include "rzg2ul-smarc-pinfunction.dtsi"
9 #include "rz-smarc-common.dtsi"
12 &canfd {
13 /delete-property/ pinctrl-0;
14 /delete-property/ pinctrl-names;
20 sound-dai = <&ssi1>;
24 wm8978: codec@1a {
26 #sound-dai-cells = <0>;
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Drz-smarc-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 * SSI-WM8978
32 stdout-path = "serial0:115200n8";
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <11289600>;
42 compatible = "simple-audio-card";
43 simple-audio-card,format = "i2s";
[all …]
Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
[all …]
Dr8a77970.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3M (R8A77970) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a77970-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
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Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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Dr8a77970-eagle.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Eagle board with R-Car V3M
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
29 stdout-path = "serial0:115200n8";
32 d3p3: regulator-fixed {
33 compatible = "regulator-fixed";
34 regulator-name = "fixed-3.3V";
35 regulator-min-microvolt = <3300000>;
[all …]
Dr8a77980.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
21 compatible = "fixed-clock";
[all …]
Dr8a77995.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
[all …]
/Linux-v6.6/drivers/net/can/
Dxilinx_can.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2012 - 2022 Xilinx, Inc.
6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
87 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
94 #define XCAN_2_BRPR_TDCO_MASK GENMASK(13, 8) /* TDCO for CANFD 2.0 */
97 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
100 #define XCAN_BTR_TS1_MASK_CANFD 0x0000003F /* Time segment 1 */
141 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
148 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
155 #define XCAN_TIMEOUT (1 * HZ)
[all …]
/Linux-v6.6/drivers/net/can/rcar/
Drcar_canfd.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8 * - CAN FD only mode
9 * - Classical CAN (CAN 2.0) only mode
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
53 #define RCANFD_GCFG_DCE BIT(1)
71 #define RCANFD_GSTS_GHLTSTS BIT(1)
73 /* Non-operational status */
74 #define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3))
[all …]
/Linux-v6.6/drivers/net/can/dev/
Ddev.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2005 Marc Kleine-Budde, Pengutronix
4 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
13 #include <linux/can/can-ml.h>
24 if (new_state <= priv->state) in can_update_state_error_stats()
29 priv->can_stats.error_warning++; in can_update_state_error_stats()
32 priv->can_stats.error_passive++; in can_update_state_error_stats()
35 priv->can_stats.bus_off++; in can_update_state_error_stats()
99 if (unlikely(new_state == priv->state)) { in can_change_state()
105 can_get_state_str(priv->state), priv->state, in can_change_state()
[all …]
/Linux-v6.6/drivers/net/can/usb/etas_es58x/
Des58x_fd.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Driver for ETAS GmbH ES58X USB CAN(-FD) Bus Interfaces.
6 * ES582.1 and ES584.1 (naming convention: we use the term "ES58X FD"
20 #define ES584_1_NUM_CAN_CH 1
34 /* Command IDs for ES58X_FD_CMD_TYPE_{CAN,CANFD}. */
54 * enum es58x_fd_ctrlmode - Controller mode.
58 * @ES58X_FD_CTRLMODE_FD: CAN FD according to ISO11898-1.
63 * dominant. (c.f. ISO 11898-1:2015, section 10.4.2.4 "Control
65 * error frame. 1 (disable): goes into bus integration mode
68 * filtering is disabled. 1: Edge filtering is enabled. Two
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/Linux-v6.6/drivers/net/can/usb/
Dgs_usb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2016 Geschwister Schneider Technologie-,
6 * Entwicklungs- und Vertriebs UG (Haftungsbeschränkt).
8 * Copyright (c) 2023 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
28 #include <linux/can/rx-offload.h>
43 #define GS_USB_ENDPOINT_IN 1
46 /* Timestamp 32 bit timer runs at 1 MHz (1 µs tick). Worker accounts
49 #define GS_USB_TIMESTAMP_TIMER_HZ (1 * HZ_PER_MHZ)
106 * Technologie Entwicklungs- und Vertriebs UG exchanges all data
129 #define GS_CAN_MODE_LOOP_BACK BIT(1)
[all …]
/Linux-v6.6/Documentation/networking/device_drivers/can/ctu/
Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
10 ------------------------
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
33 version of emulation support can be cloned from ctu-canfd branch of QEMU local
34 development `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
38 ---------------
59 it allows for device hot-plug.
[all …]
/Linux-v6.6/include/linux/can/dev/
Dpeak_canfd.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * CAN driver for PEAK System micro-CAN based adapters
5 * Copyright (C) 2003-2011 PEAK System-Technik GmbH
6 * Copyright (C) 2011-2013 Stephane Grosjean <s.grosjean@peak-system.com>
11 /* uCAN commands opcodes list (low-order 10 bits) */
48 return le16_to_cpu(c->opcode_channel) & 0x3ff; in pucan_cmd_get_opcode()
56 #define PUCAN_TSLOW_BRP_MASK ((1 << PUCAN_TSLOW_BRP_BITS) - 1)
57 #define PUCAN_TSLOW_TSEG1_MASK ((1 << PUCAN_TSLOW_TSGEG1_BITS) - 1)
58 #define PUCAN_TSLOW_TSEG2_MASK ((1 << PUCAN_TSLOW_TSGEG2_BITS) - 1)
59 #define PUCAN_TSLOW_SJW_MASK ((1 << PUCAN_TSLOW_SJW_BITS) - 1)
[all …]
/Linux-v6.6/arch/arm64/boot/dts/freescale/
Dimx8mm-mx8menlo.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
6 /dts-v1/;
8 #include "imx8mm-verdin.dtsi"
13 "toradex,verdin-imx8mm-nonwifi",
14 "toradex,verdin-imx8mm",
17 /delete-node/ gpio-keys;
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_led>;
[all …]
/Linux-v6.6/include/uapi/linux/
Dif_ether.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
9 * Version: @(#)if_ether.h 1.0.1a 02/08/94
58 #define ETH_P_BATMAN 0x4305 /* B.A.T.M.A.N.-Advanced packet [ NOT AN OFFICIALLY REGISTERED ID ] */
77 #define ETH_P_WCCP 0x883E /* Web-cache coordination protocol
78 * defined in draft-wilson-wrec-wccp-v2-00.txt */
85 #define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport
94 #define ETH_P_802_EX1 0x88B5 /* 802.1 Local Experimental 1. */
104 #define ETH_P_PRP 0x88FB /* IEC 62439-3 PRP/HSRv0 */
111 #define ETH_P_HSR 0x892F /* IEC 62439-3 HSRv1 */
120 #define ETH_P_IFE 0xED3E /* ForCES inter-FE LFB type */
[all …]
/Linux-v6.6/drivers/clk/renesas/
Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
53 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
75 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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