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/Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/
D	cache.json	611 …te Intel Optane DC persistent memory as the data source where the data request missed all caches.", 725 …al Intel Optane DC persistent memory as the data source where the data request missed all caches.", 756 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 767 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 778 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 789 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 800 …demand data reads that hit in the L3 or were snooped from another core's caches on the same socket… 811 …ata reads that resulted in a snoop hit a modified line in another core's caches which forwarded th… 833 …"Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded th… 844 …e on a remote socket where a snoop hit a modified line in another core's caches which forwarded th… [all …]
D	memory.json	214 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 225 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 236 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 247 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 258 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 269 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … 280 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … 291 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that mi… 302 …BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", 313 …eaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline …
D	other.json	211 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 233 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that ha… 244 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 255 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 266 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 277 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 288 …demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's … 299 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 310 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 321 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… [all …]
/Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/
D	other.json	45 …as found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single s… 56 …m this core's caches, after the data is forwarded back to the requestor, and indicating the data w… 67 …his core's caches without being forwarded back to the requestor. The line was in Forward, Shared o… 78 … to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop re… 391 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 402 …writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 424 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that ha… 435 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 446 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… 457 … code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that we… [all …]
D	memory.json	155 …1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", 166 …he prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 177 …on": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", 188 …nd data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 199 …xclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 210 …p (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied … 221 … prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", 232 …pt PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … 243 … "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", 254 …o the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline … [all …]
D	cache.json	529 …te Intel Optane DC persistent memory as the data source where the data request missed all caches.", 646 …al Intel Optane DC persistent memory as the data source where the data request missed all caches.", 659 … cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket… 670 …refetches that resulted in a snoop hit a modified line in another core's caches which forwarded th… 681 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 692 …d line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket whe… 703 …demand data reads that hit in the L3 or were snooped from another core's caches on the same socket… 714 …ata reads that resulted in a snoop hit a modified line in another core's caches which forwarded th… 736 …"Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded th… 747 …e on a remote socket where a snoop hit a modified line in another core's caches which forwarded th… [all …]
/Linux-v6.1/Documentation/block/
D	writeback_cache_control.rst	`9 write back caches. That means the devices signal I/O completion to the 60 devices with volatile caches need to implement the support for these 67 For devices that do not support volatile write caches there is no driver 70 requests that have a payload. For devices with volatile write caches the 71 driver needs to tell the block layer that it supports flushing caches by`
/Linux-v6.1/arch/sparc/include/asm/
D	viking.h	27 * and never caches them internally (or so states the docs). Therefore 38 * on chip split I/D caches of the GNU/Viking. 45 * caches will snoop regardless of whether they are enabled, this 46 * takes care of the case where the I or D or both caches are turned 58 * caches, they may be cached by the GNU/MXCC if present and enabled. 72 * caches during that cycle. If disabled, all stores operations 78 * These bits enable the on-cpu GNU/Viking split I/D caches. Note, 79 * as mentioned above, these caches will snoop the bus in GNU/MBUS
/Linux-v6.1/Documentation/filesystems/nfs/
D	rpc-cache.rst	`9 Caches chapter 13 a wide variety of values to be caches. 15 There are a number of caches that are similar in structure though 17 of common code for managing these caches. 19 Examples of caches that are likely to be needed are: 105 includes it on a list of caches that will be regularly`
/Linux-v6.1/kernel/bpf/
D	memalloc.c	410 ma->caches = pcc; in bpf_mem_alloc_init() 438 free_percpu(ma->caches); in free_mem_alloc_no_barrier() 440 ma->caches = NULL; in free_mem_alloc_no_barrier() 446 * still execute. Wait for it now before we freeing percpu caches. in free_mem_alloc() 483 copy->caches = ma->caches; in destroy_mem_alloc() 484 ma->caches = NULL; in destroy_mem_alloc() 517 if (ma->caches) { in bpf_mem_alloc_destroy() 520 cc = per_cpu_ptr(ma->caches, cpu); in bpf_mem_alloc_destroy() 617 ret = unit_alloc(this_cpu_ptr(ma->caches)->cache + idx); in bpf_mem_alloc() 632 unit_free(this_cpu_ptr(ma->caches)->cache + idx, ptr); in bpf_mem_free()
/Linux-v6.1/arch/openrisc/
D	Kconfig	`80 bool "Have write through data caches" 83 Select this if your implementation features write through data caches. 85 caches at relevant times. Most OpenRISC implementations support write- 86 through data caches.`
/Linux-v6.1/include/linux/
D	kvm_types.h	`83 * Memory caches are used to preallocate memory ahead of various MMU flows, 86 * holding MMU locks. Note, these caches act more like prefetch buffers than 87 * classical caches, i.e. objects are not returned to the cache on being freed.`
/Linux-v6.1/arch/arm64/kernel/
D	cacheinfo.c	`58 /* Separate instruction and data caches / in init_cache_level() 72 some external caches not specified in CLIDR_EL1 in init_cache_level() 74 * only unified external caches are considered here in init_cache_level()`
/Linux-v6.1/arch/mips/kernel/
D	bmips_5xxx_init.S	`300 * Description: Enable I and D caches, initialize I and D-caches, also set 323 * Description: Enable I and D caches, and initialize I and D-caches 344 /* Enable Caches before Clearing. If the caches are disabled 715 * Description: Enable I and D caches, and initialize I and D-caches`
/Linux-v6.1/arch/mips/include/asm/
D	io.h	498 * The caches on some architectures aren't dma-coherent and have need to 502 * - dma_cache_wback_inv(start, size) makes caches and coherent by 503 * writing the content of the caches back to memory, if necessary. 504 * The function also invalidates the affected part of the caches as 506 * - dma_cache_wback(start, size) makes caches and coherent by 507 * writing the content of the caches back to memory, if necessary. 508 * The function also invalidates the affected part of the caches as 511 * caches. Dirty lines of the caches may be written back or simply
/Linux-v6.1/tools/cgroup/
D	memcg_slabinfo.py	`184 caches = {} 203 caches[addr] = cache 215 for addr in caches: 217 cache_show(caches[addr], cfg, stats[addr])`
/Linux-v6.1/arch/mips/mm/
D	c-r4k.c	75 * separate caches). in r4k_op_needs_ipi() 498 * These caches are inclusive caches, that is, if something in local_r4k___flush_cache_all() 500 * in one of the primary caches. in local_r4k___flush_cache_all() 579 * whole caches when vma is executable. 619 * only flush the primary caches but R1x000 behave sane ... in local_r4k_flush_cache_mm() 621 * caches, so we can bail out early. in local_r4k_flush_cache_mm() 880 * Either no secondary cache or the available caches don't have the in r4k_dma_cache_wback_inv() 881 * subset property so we have to flush the primary caches in r4k_dma_cache_wback_inv() 984 * Aliases only affect the primary caches so don't bother with in local_r4k_flush_kernel_vmap_range_index() 985 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range_index() [all …]
/Linux-v6.1/arch/powerpc/platforms/52xx/
D	lite5200_sleep.S	`72 /* flush caches [destroys r3, r4] / 93 / disable I and D caches / 226 / invalidate caches / 229 mtspr SPRN_HID0, r5 / invalidate caches / 234 / enable caches / 236 mtspr SPRN_HID0, r10 / restore (enable caches, DPM) */`
/Linux-v6.1/arch/arm/mm/
D	proc-sa1100.S	`50 * - Clean and turn off caches. 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 120 * Clean the specified entry of any caches such that the MMU 201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4`
D	proc-arm926.S	`53 mcr p15, 0, r0, c1, c0, 0 @ disable caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 184 * Harvard caches, you need to implement this function. 197 * Harvard caches, you need to implement this function. 404 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 425 mov r0, #4 @ disable write-back on caches explicitly`
D	proc-sa110.S	`49 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 * Clean the specified entry of any caches such that the MMU 162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4`
/Linux-v6.1/arch/powerpc/boot/
D	gamecube-head.S	`14 * - if the data and instruction caches are enabled or not 17 * We enable the caches if not already enabled, enable the MMU with an 75 /* enable and invalidate the caches if not already enabled */`
/Linux-v6.1/drivers/gpu/drm/i915/gem/
D	i915_gem_object_types.h	172 * The Gfx L3 sits between the domain specific caches, e.g 173 * sampler/render caches, and the larger LLC. LLC is coherent with the 188 * The GPU can utilise the caches, while still having the display engine 190 * CPU caches when moving out of the render domain. This is the default 361 * writing through the CPU caches. The largely depends on the 373 * access will automatically snoop the CPU caches(even with CACHE_NONE). 376 * surface out of the CPU caches when preparing it for scanout. Also 495 * These monitor which caches contain read/write data related to the 497 * the driver is called to ensure that caches are suitably flushed and
/Linux-v6.1/arch/arm/boot/compressed/
D	head-xscale.S	`28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches 30 @ disabling MMU and caches`
/Linux-v6.1/Documentation/core-api/
D	cachetlb.rst	`121 us to properly handle systems whose caches are strict and require 129 indexed caches which must be flushed when virtual-->physical 131 indexed physically tagged caches of IA32 processors have no need to 132 implement these interfaces since the caches are fully synchronized 140 the caches. That is, after running, there will be no cache 149 the caches. That is, after running, there will be no cache 156 optimizations for VIPT caches.`

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