Searched +full:c900 +full:- +full:plic (Results 1 – 2 of 2) sorted by relevance
/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/ |
D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 4 --- 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: SiFive Platform-Level Interrupt Controller (PLIC) 11 SiFive SoCs and other RISC-V SoCs include an implementation of the 12 Platform-Level Interrupt Controller (PLIC) high-level specification in 13 the RISC-V Privileged Architecture specification. The PLIC connects all 18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 21 Each interrupt can be enabled on per-context basis. Any context can claim [all …]
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/Linux-v6.1/drivers/irqchip/ |
D | irq-sifive-plic.c | 1 // SPDX-License-Identifier: GPL-2.0 6 #define pr_fmt(fmt) "plic: " fmt 23 * This driver implements a version of the RISC-V PLIC with the actual layout 26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf 28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is 29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged 102 raw_spin_lock(&handler->enable_lock); in plic_toggle() 103 __plic_toggle(handler->enable_base, hwirq, enable); in plic_toggle() 104 raw_spin_unlock(&handler->enable_lock); in plic_toggle() 115 plic_toggle(handler, d->hwirq, enable); in plic_irq_toggle() [all …]
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