| /Linux-v5.10/sound/soc/codecs/ |
| D | wm8990.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8990.c -- WM8990 ALSA Soc Audio driver
37 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
39 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
41 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
43 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
45 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
47 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
54 (struct soc_mixer_control *)kcontrol->private_value; in wm899x_outpga_put_volsw_vu()
55 int reg = mc->reg; in wm899x_outpga_put_volsw_vu()
[all …]
|
| D | wm8991.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8991.c -- WM8991 ALSA Soc Audio driver
5 * Copyright 2007-2010 Wolfson Microelectronics PLC.
23 #include <sound/soc-dapm.h>
36 { 1, 0x0000 }, /* R1 - Power Management (1) */
37 { 2, 0x6000 }, /* R2 - Power Management (2) */
38 { 3, 0x0000 }, /* R3 - Power Management (3) */
39 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
40 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
41 { 6, 0x01C8 }, /* R6 - Clocking (1) */
[all …]
|
| D | wm8400.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8400.c -- WM8400 ALSA Soc Audio driver
5 * Copyright 2008-11 Wolfson Microelectronics PLC.
18 #include <linux/mfd/wm8400-audio.h>
19 #include <linux/mfd/wm8400-private.h>
67 wm8400_reset_codec_reg_cache(wm8400->wm8400); in wm8400_component_reset()
70 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
72 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
74 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
76 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
[all …]
|
| D | isabelle.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * isabelle.c - Low power high fidelity audio codec driver
22 #include <sound/soc-dapm.h>
342 static const DECLARE_TLV_DB_SCALE(afm_amp_tlv, -3300, 300, 0);
343 static const DECLARE_TLV_DB_SCALE(dac_tlv, -1200, 200, 0);
344 static const DECLARE_TLV_DB_SCALE(hf_tlv, -5000, 200, 0);
346 /* from -63 to 0 dB in 1 dB steps */
347 static const DECLARE_TLV_DB_SCALE(dpga_tlv, -6300, 100, 1);
349 /* from -63 to 9 dB in 1 dB steps */
350 static const DECLARE_TLV_DB_SCALE(rx_tlv, -6300, 100, 1);
[all …]
|
| D | adau1761.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
125 static const DECLARE_TLV_DB_SCALE(adau1761_sing_in_tlv, -1500, 300, 1);
126 static const DECLARE_TLV_DB_SCALE(adau1761_diff_in_tlv, -1200, 75, 0);
127 static const DECLARE_TLV_DB_SCALE(adau1761_out_tlv, -5700, 100, 0);
128 static const DECLARE_TLV_DB_SCALE(adau1761_sidetone_tlv, -1800, 300, 1);
129 static const DECLARE_TLV_DB_SCALE(adau1761_boost_tlv, -600, 600, 1);
130 static const DECLARE_TLV_DB_SCALE(adau1761_pga_boost_tlv, -2000, 2000, 1);
132 static const DECLARE_TLV_DB_SCALE(adau1761_alc_max_gain_tlv, -1200, 600, 0);
[all …]
|
| D | tlv320dac33.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <sound/tlv320dac33-plat.h>
49 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate))))
115 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
116 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
117 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
118 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
119 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
120 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
121 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
[all …]
|
| D | wm8955.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8955.c -- WM8955 ALSA SoC Audio driver
50 { 2, 0x0079 }, /* R2 - LOUT1 volume */
51 { 3, 0x0079 }, /* R3 - ROUT1 volume */
52 { 5, 0x0008 }, /* R5 - DAC Control */
53 { 7, 0x000A }, /* R7 - Audio Interface */
54 { 8, 0x0000 }, /* R8 - Sample Rate */
55 { 10, 0x00FF }, /* R10 - Left DAC volume */
56 { 11, 0x00FF }, /* R11 - Right DAC volume */
57 { 12, 0x000F }, /* R12 - Bass control */
[all …]
|
| /Linux-v5.10/drivers/regulator/ |
| D | anatop-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0+
30 bool bypass; member
43 if (anatop_reg->delay_bit_width && new_sel > old_sel) { in anatop_regmap_set_voltage_time_sel()
50 regmap_read(reg->regmap, anatop_reg->delay_reg, &val); in anatop_regmap_set_voltage_time_sel()
51 val = (val >> anatop_reg->delay_bit_shift) & in anatop_regmap_set_voltage_time_sel()
52 ((1 << anatop_reg->delay_bit_width) - 1); in anatop_regmap_set_voltage_time_sel()
53 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << in anatop_regmap_set_voltage_time_sel()
65 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
85 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
86 anatop_reg->sel = selector; in anatop_regmap_core_set_voltage_sel()
[all …]
|
| /Linux-v5.10/drivers/base/regmap/ |
| D | regcache.c | 1 // SPDX-License-Identifier: GPL-2.0
34 if (!map->num_reg_defaults_raw) in regcache_hw_init()
35 return -EINVAL; in regcache_hw_init()
38 for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) in regcache_hw_init()
39 if (regmap_readable(map, i * map->reg_stride) && in regcache_hw_init()
40 !regmap_volatile(map, i * map->reg_stride)) in regcache_hw_init()
43 /* all registers are unreadable or volatile, so just bypass */ in regcache_hw_init()
45 map->cache_bypass = true; in regcache_hw_init()
49 map->num_reg_defaults = count; in regcache_hw_init()
50 map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), in regcache_hw_init()
[all …]
|
| /Linux-v5.10/drivers/clk/ti/ |
| D | dpll3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
[all …]
|
| D | clkt_dpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
17 #include <linux/clk-provider.h>
30 #define DPLL_MULT_UNDERFLOW -1
51 #define DPLL_FINT_UNDERFLOW -1
52 #define DPLL_FINT_INVALID -2
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
63 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate
[all …]
|
| /Linux-v5.10/drivers/dma/fsl-dpaa2-qdma/ |
| D | dpaa2-qdma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 u32 rbpcmd; /* Route-by-port command */
36 #define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */
37 #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
38 #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
43 #define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */
51 #define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */
62 #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
63 #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
110 * dpaa2_qdma_priv - driver private data
|
| /Linux-v5.10/Documentation/devicetree/bindings/regulator/ |
| D | ti-abb-regulator.txt | 4 - compatible: Should be one of:
5 - "ti,abb-v1" for older SoCs like OMAP3
6 - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
7 - "ti,abb-v3" for a generic definition where setup and control registers are
9 - reg: Address and length of the register set for the device. It contains
10 the information of registers in the same order as described by reg-names
11 - reg-names: Should contain the reg names
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
[all …]
|
| /Linux-v5.10/include/linux/clk/ |
| D | ti.h | 18 #include <linux/clk-provider.h>
22 * struct clk_omap_reg - OMAP register declaration
34 * struct dpll_data - DPLL registers and integration data
38 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
48 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
50 * @min_divider: minimum valid non-bypass divider value (actual)
51 * @max_divider: maximum valid non-bypass divider value (actual)
61 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
63 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
69 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
[all …]
|
| /Linux-v5.10/drivers/iommu/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
6 # The IOASID library may also be used by non-IOMMU_API users
37 Enable support for the ARM long descriptor pagetable format.
39 sizes at both stage-1 and stage-2, as well as address spaces
40 up to 48-bits in size.
46 Enable self-tests for LPAE page table allocator. This performs
47 a series of page-table consistency checks during boot.
56 Enable support for the ARM Short-descriptor pagetable format.
57 This supports 32-bit virtual and physical addresses mapped using
[all …]
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_link_encoder.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
41 enc10->base.ctx
43 enc10->base.ctx->logger
46 (enc10->link_regs->reg)
50 enc10->link_shift->field_name, enc10->link_mask->field_name
56 * ASIC-dependent, actual values for register programming
102 struct dc_bios *bp = enc10->base.ctx->dc_bios; in link_transmitter_control()
104 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control()
111 bool enable) in enable_phy_bypass_mode() argument
116 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); in enable_phy_bypass_mode()
[all …]
|
| /Linux-v5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
61 enc110->base.ctx
63 enc110->base.ctx->logger
66 (enc110->link_regs->reg)
69 (enc110->aux_regs->reg)
72 (enc110->hpd_regs->reg)
79 * ASIC-dependent, actual values for register programming
95 (reg + enc110->offsets.dig)
98 (reg + enc110->offsets.dp)
130 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
[all …]
|
| /Linux-v5.10/arch/arm/mach-davinci/ |
| D | sleep.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
41 stmfd sp!, {r0-r12, lr} @ save registers on stack
46 ldmia r0, {r0-r4}
49 * Switch DDR to self-refresh mode.
77 /* Put the DDR PLL in bypass and power down */
83 /* Wait for PLL to switch to bypass */
101 /* Clear sleep enable */
132 /* Remove PLL from bypass mode */
144 /* Enable VCLK */
146 /* Enable DDR2 LPSC */
[all …]
|
| /Linux-v5.10/drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_dcb_82599.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * 1 WSP - Weighted Strict Priority
12 * 1 WRR - Weighted Round Robin
16 #define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
17 #define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
30 #define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
31 #define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
34 * buffers enable
37 * (RSS) enable
[all …]
|
| /Linux-v5.10/drivers/net/ethernet/cavium/thunder/ |
| D | thunder_xcv.c | 1 // SPDX-License-Identifier: GPL-2.0-only
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
81 /* Configure DLL - enable or bypass in xcv_init_hw()
82 * TX no bypass, RX bypass in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
87 writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
89 /* Enable compensation controller and force the in xcv_init_hw()
[all …]
|
| /Linux-v5.10/drivers/clk/qcom/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
46 * H/W requires a 5us delay between disabling the bypass and in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
[all …]
|
| D | clk-hfpll.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
12 #include "clk-regmap.h"
13 #include "clk-hfpll.h"
19 /* Initialize a HFPLL at a given rate and enable it. */
23 struct hfpll_data const *hd = h->d; in __clk_hfpll_init_once()
24 struct regmap *regmap = h->clkr.regmap; in __clk_hfpll_init_once()
26 if (likely(h->init_done)) in __clk_hfpll_init_once()
30 if (hd->config_val) in __clk_hfpll_init_once()
31 regmap_write(regmap, hd->config_reg, hd->config_val); in __clk_hfpll_init_once()
[all …]
|
| /Linux-v5.10/Documentation/devicetree/bindings/power/supply/ |
| D | bq25980.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Dan Murphy <dmurphy@ti.com>
12 - Ricardo Rivera-Matos <r-rivera-matos@ti.com>
16 for use in high-power density portable electronics. These inductorless
21 - $ref: power-supply.yaml#
26 - ti,bq25980
27 - ti,bq25975
28 - ti,bq25960
[all …]
|
| /Linux-v5.10/Documentation/admin-guide/device-mapper/ |
| D | dm-dust.rst | 1 dm-dust
5 locations, and the ability to enable the emulation of the failures
27 With dm-dust, the user can use the "addbadblock" and "removebadblock"
29 "enable" and "disable" messages to modulate the state of whether the
31 This allows the pre-writing of test data and metadata prior to
35 ----------------
51 ------------------
53 First, find the size (in 512-byte sectors) of the device to be used::
55 $ sudo blockdev --getsz /dev/vdb1
58 Create the dm-dust device:
[all …]
|
| /Linux-v5.10/virt/lib/ |
| D | irqbypass.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * IRQ offload/bypass manager
10 * Interrupts on Intel VT-d systems can allow interrupts to be received
13 * interrupt producers and consumers to find each other to enable this sort of
14 * bypass.
23 MODULE_DESCRIPTION("IRQ bypass manager utility module");
35 if (prod->stop) in __connect()
36 prod->stop(prod); in __connect()
37 if (cons->stop) in __connect()
38 cons->stop(cons); in __connect()
[all …]
|
