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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
15 responsible for the chip subsystems clocking and resetting. The CCU is
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
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Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
15 responsible for the chip subsystems clocking and resetting. The CCU is
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
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/Linux-v6.1/drivers/clk/baikal-t1/
Dclk-ccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
27 #include <dt-bindings/clock/bt1-ccu.h>
29 #include "ccu-div.h"
30 #include "ccu-rst.h"
125 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
128 * the later is clocking the AXI-bus between DDR controller and the Main
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Dccu-rst.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 CCU Resets interface driver
11 #define pr_fmt(fmt) "bt1-ccu-rst: " fmt
19 #include <linux/reset-controller.h>
22 #include <dt-bindings/reset/bt1-ccu.h>
24 #include "ccu-rst.h"
66 * Each AXI-bus clock divider is equipped with the corresponding clock-consumer
67 * domain reset (it's self-deasserted reset control).
84 * SATA reference clock domain and APB-bus domain are connected with the
85 * sefl-deasserted reset control, which can be activated via the corresponding
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Dclk-ccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL clocks driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
18 #include <linux/clk-provider.h>
25 #include <dt-bindings/clock/bt1-ccu.h>
27 #include "ccu-pll.h"
59 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
60 * DDR controller AXI-bus clocks. If they are gated the system will be
62 * of the corresponding subsystems. So until we aren't ready to re-initialize
93 return data->plls[idx]; in ccu_pll_find_desc()
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Dccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
114 return -EINVAL; in ccu_pll_enable()
117 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_enable()
121 spin_lock_irqsave(&pll->lock, flags); in ccu_pll_enable()
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Dccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers interface driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
19 #include <linux/clk-provider.h>
27 #include "ccu-div.h"
35 GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
48 * getter available with non-constant mask support.
87 if (div->features & CCU_DIV_LOCK_SHIFTED) in ccu_div_var_update_clkdiv()
92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
96 * Until there is nsec-version of readl_poll_timeout() is available in ccu_div_var_update_clkdiv()
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