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/Linux-v5.10/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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/Linux-v5.10/Documentation/devicetree/bindings/bus/
Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
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Dbaikal,bt1-apb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 APB-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
15 which routes them to the AXI-APB bridge. This interface is a single master
22 - $ref: /schemas/simple-bus.yaml#
27 const: baikal,bt1-apb
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/Linux-v5.10/drivers/bus/
Dbt1-axi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 AXI-bus driver
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
37 * @qos_regs: AXI Interconnect QoS tuning registers.
38 * @sys_regs: Baikal-T1 System Controller registers map.
40 * @aclk: AXI reference clock.
41 * @arst: AXI Interconnect reset line.
60 struct bt1_axi *axi = data; in bt1_axi_isr() local
63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()
64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-$(CONFIG_ARM_CCI) += arm-cci.o
8 obj-$(CONFIG_ARM_INTEGRATOR_LM) += arm-integrator-lm.o
9 obj-$(CONFIG_HISILICON_LPC) += hisi_lpc.o
10 obj-$(CONFIG_BRCMSTB_GISB_ARB) += brcmstb_gisb.o
11 obj-$(CONFIG_MOXTET) += moxtet.o
13 # DPAA2 fsl-mc bus
14 obj-$(CONFIG_FSL_MC_BUS) += fsl-mc/
16 obj-$(CONFIG_BT1_APB) += bt1-apb.o
17 obj-$(CONFIG_BT1_AXI) += bt1-axi.o
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/Linux-v5.10/drivers/clk/baikal-t1/
Dclk-ccu-div.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU Dividers clock driver
12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
17 #include <linux/clk-provider.h>
18 #include <linux/reset-controller.h>
26 #include <dt-bindings/clock/bt1-ccu.h>
27 #include <dt-bindings/reset/bt1-ccu.h>
29 #include "ccu-div.h"
128 * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
131 * the later is clocking the AXI-bus between DDR controller and the Main
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Dclk-ccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL clocks driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
17 #include <linux/clk-provider.h>
24 #include <dt-bindings/clock/bt1-ccu.h>
26 #include "ccu-pll.h"
56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
57 * DDR controller AXI-bus clocks. If they are gated the system will be
59 * of the corresponding subsystems. So until we aren't ready to re-initialize
88 pll = data->plls[idx]; in ccu_pll_find_desc()
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/Linux-v5.10/drivers/spi/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG
8 # small core, mostly translating board-specific
10 obj-$(CONFIG_SPI_MASTER) += spi.o
11 obj-$(CONFIG_SPI_MEM) += spi-mem.o
12 obj-$(CONFIG_SPI_MUX) += spi-mux.o
13 obj-$(CONFIG_SPI_SPIDEV) += spidev.o
14 obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
17 obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
18 obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o
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/Linux-v5.10/drivers/hwmon/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_HWMON) += hwmon.o
7 obj-$(CONFIG_HWMON_VID) += hwmon-vid.o
10 obj-$(CONFIG_SENSORS_ACPI_POWER) += acpi_power_meter.o
11 obj-$(CONFIG_SENSORS_ATK0110) += asus_atk0110.o
15 obj-$(CONFIG_SENSORS_ASB100) += asb100.o
16 obj-$(CONFIG_SENSORS_W83627HF) += w83627hf.o
17 obj-$(CONFIG_SENSORS_W83773G) += w83773g.o
18 obj-$(CONFIG_SENSORS_W83792D) += w83792d.o
19 obj-$(CONFIG_SENSORS_W83793) += w83793.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 sensors-detect script from the lm_sensors package. Read
21 <file:Documentation/hwmon/userspace-tools.rst> for details.
52 will be called abx500-temp.
267 will be called as370-hwmon.
287 AXI HDL FAN monitoring core.
290 will be called axi-fan-control
299 lm-sensors 2.10.1 for proper userspace support.
348 Only Intel-based Apple's computers are supported (MacBook Pro,
355 the laptop to act as a pinball machine-esque joystick.
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