Searched full:bit (Results 1 – 25 of 6388) sorted by relevance
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63 #define NH_FLD_ETH_DA BIT(0)64 #define NH_FLD_ETH_SA BIT(1)65 #define NH_FLD_ETH_LENGTH BIT(2)66 #define NH_FLD_ETH_TYPE BIT(3)67 #define NH_FLD_ETH_FINAL_CKSUM BIT(4)68 #define NH_FLD_ETH_PADDING BIT(5)69 #define NH_FLD_ETH_ALL_FIELDS (BIT(6) - 1)72 #define NH_FLD_VLAN_VPRI BIT(0)73 #define NH_FLD_VLAN_CFI BIT(1)74 #define NH_FLD_VLAN_VID BIT(2)[all …]
171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31)172 #define QCA956X_MAC_CFG1_RX_RST BIT(19)173 #define QCA956X_MAC_CFG1_TX_RST BIT(18)174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8)175 #define QCA956X_MAC_CFG1_RX_EN BIT(2)176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9)180 #define QCA956X_MAC_CFG2_IF_10_100 BIT(8)181 #define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)182 #define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)[all …]
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)17 #define DSI_MCTL_MAIN_DATA_CTL_BTA_EN BIT(9)[all …]
83 #define AB8500_TURNONSTATUS_PORNVBAT BIT(0)84 #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)85 #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)86 #define AB8500_TURNONSTATUS_RTCALARM BIT(3)87 #define AB8500_TURNONSTATUS_MAINCHDET BIT(4)88 #define AB8500_TURNONSTATUS_VBUSDET BIT(5)89 #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)91 #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)92 #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)97 #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)[all …]
44 #define PME_ENABLE BIT(1)45 #define PME_POLARITY BIT(0)49 #define SW_GIGABIT_ABLE BIT(6)50 #define SW_REDUNDANCY_ABLE BIT(5)51 #define SW_AVB_ABLE BIT(4)69 #define SW_QW_ABLE BIT(5)75 #define LUE_INT BIT(31)76 #define TRIG_TS_INT BIT(30)77 #define APB_TIMEOUT_INT BIT(29)88 #define SW_SPARE_REG_2 BIT(7)[all …]
34 #define SW_NEW_BACKOFF BIT(7)35 #define SW_GLOBAL_RESET BIT(6)36 #define SW_FLUSH_DYN_MAC_TABLE BIT(5)37 #define SW_FLUSH_STA_MAC_TABLE BIT(4)38 #define SW_LINK_AUTO_AGING BIT(0)42 #define SW_HUGE_PACKET BIT(6)43 #define SW_TX_FLOW_CTRL_DISABLE BIT(5)44 #define SW_RX_FLOW_CTRL_DISABLE BIT(4)45 #define SW_CHECK_LENGTH BIT(3)46 #define SW_AGING_ENABLE BIT(2)[all …]
13 #define FUSB_REG_SWITCHES0_CC2_PU_EN BIT(7)14 #define FUSB_REG_SWITCHES0_CC1_PU_EN BIT(6)15 #define FUSB_REG_SWITCHES0_VCONN_CC2 BIT(5)16 #define FUSB_REG_SWITCHES0_VCONN_CC1 BIT(4)17 #define FUSB_REG_SWITCHES0_MEAS_CC2 BIT(3)18 #define FUSB_REG_SWITCHES0_MEAS_CC1 BIT(2)19 #define FUSB_REG_SWITCHES0_CC2_PD_EN BIT(1)20 #define FUSB_REG_SWITCHES0_CC1_PD_EN BIT(0)22 #define FUSB_REG_SWITCHES1_POWERROLE BIT(7)23 #define FUSB_REG_SWITCHES1_SPECREV1 BIT(6)[all …]
10 #define SYS_ISO_MD2PP BIT(0)11 #define SYS_ISO_ANALOG_IPS BIT(5)12 #define SYS_ISO_DIOR BIT(9)13 #define SYS_ISO_PWC_EV25V BIT(14)14 #define SYS_ISO_PWC_EV12V BIT(15)17 #define SYS_FUNC_BBRSTB BIT(0)18 #define SYS_FUNC_BB_GLB_RSTN BIT(1)19 #define SYS_FUNC_USBA BIT(2)20 #define SYS_FUNC_UPLL BIT(3)21 #define SYS_FUNC_USBD BIT(4)[all …]
44 #define GOTGCTL_CHIRPEN BIT(27)47 #define GOTGCTL_OTGVER BIT(20)48 #define GOTGCTL_BSESVLD BIT(19)49 #define GOTGCTL_ASESVLD BIT(18)50 #define GOTGCTL_DBNC_SHORT BIT(17)51 #define GOTGCTL_CONID_B BIT(16)52 #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)53 #define GOTGCTL_DEVHNPEN BIT(11)54 #define GOTGCTL_HSTSETHNPEN BIT(10)55 #define GOTGCTL_HNPREQ BIT(9)[all …]
76 #define LP873X_BUCK0_CTRL_1_BUCK0_FPWM BIT(3)77 #define LP873X_BUCK0_CTRL_1_BUCK0_RDIS_EN BIT(2)78 #define LP873X_BUCK0_CTRL_1_BUCK0_EN_PIN_CTRL BIT(1)79 #define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0)84 #define LP873X_BUCK1_CTRL_1_BUCK1_FPWM BIT(3)85 #define LP873X_BUCK1_CTRL_1_BUCK1_RDIS_EN BIT(2)86 #define LP873X_BUCK1_CTRL_1_BUCK1_EN_PIN_CTRL BIT(1)87 #define LP873X_BUCK1_CTRL_1_BUCK1_EN BIT(0)96 #define LP873X_LDO0_CTRL_LDO0_RDIS_EN BIT(2)97 #define LP873X_LDO0_CTRL_LDO0_EN_PIN_CTRL BIT(1)[all …]
96 #define LP87565_BUCK_CTRL_1_EN BIT(7)97 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)100 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)101 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)102 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)104 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)118 #define LP87565_RESET_SW_RESET BIT(0)120 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)121 #define LP87565_CONFIG_CLKIN_PD BIT(6)122 #define LP87565_CONFIG_EN4_PD BIT(5)[all …]
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)26 #define NISTC_INTA_ACK_G0_TC BIT(14)27 #define NISTC_INTA_ACK_AI_ERR BIT(13)28 #define NISTC_INTA_ACK_AI_STOP BIT(12)29 #define NISTC_INTA_ACK_AI_START BIT(11)30 #define NISTC_INTA_ACK_AI_START2 BIT(10)31 #define NISTC_INTA_ACK_AI_START1 BIT(9)32 #define NISTC_INTA_ACK_AI_SC_TC BIT(8)33 #define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7)34 #define NISTC_INTA_ACK_G0_TC_ERR BIT(6)[all …]
9 #define BIT_FEN_CPUEN BIT(2)10 #define BIT_FEN_BB_GLB_RST BIT(1)11 #define BIT_FEN_BB_RSTB BIT(0)14 #define BIT_CPU_CLK_EN BIT(14)19 #define BITS_RFC_DIRECT (BIT(31) | BIT(30))20 #define BIT_WLMCU_IOIF BIT(0)22 #define BIT_RF_SDM_RSTB BIT(2)23 #define BIT_RF_RSTB BIT(1)24 #define BIT_RF_EN BIT(0)27 #define BIT_MAC_CLK_SEL (BIT(20) | BIT(21))[all …]
26 #define BIT_FD_GMM BIT(3)27 #define BIT_FD_ISH BIT(4)32 #define BIT_LPC_CLOCK_RUN BIT(4)33 #define BIT_SHARED_IRQ_GPSC BIT(5)34 #define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)35 #define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)36 #define BIT_SHARED_IRQ_GPSS BIT(20)56 #define PMC_PSS_BIT_GBE BIT(0)57 #define PMC_PSS_BIT_SATA BIT(1)58 #define PMC_PSS_BIT_HDA BIT(2)[all …]
19 #define UART0_USE_PWM23 BIT(28)20 #define UART0_USE_PWM01 BIT(27)21 #define UART1_USE_LCD0_5_6_11 BIT(26)22 #define I2C2_USE_CAN1 BIT(25)23 #define I2C1_USE_CAN0 BIT(24)24 #define NAND3_USE_UART5 BIT(23)25 #define NAND3_USE_UART4 BIT(22)26 #define NAND3_USE_UART1_DAT BIT(21)27 #define NAND3_USE_UART1_CTS BIT(20)28 #define NAND3_USE_PWM23 BIT(19)[all …]
35 #define BIT_SYS_CTRL1_OTPVMUTEOVR_SET BIT(7)36 #define BIT_SYS_CTRL1_VSYNCPIN BIT(6)37 #define BIT_SYS_CTRL1_OTPADROPOVR_SET BIT(5)38 #define BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD BIT(4)39 #define BIT_SYS_CTRL1_OTP2XVOVR_EN BIT(3)40 #define BIT_SYS_CTRL1_OTP2XAOVR_EN BIT(2)41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)42 #define BIT_SYS_CTRL1_OTPAMUTEOVR_SET BIT(0)46 #define BIT_DPD_PWRON_PLL BIT(7)47 #define BIT_DPD_PDNTX12 BIT(6)[all …]
339 #define RXERR_RPT_RST BIT(27)443 #define CmdEEPROM_En BIT(5)445 #define CmdEERPOMSEL BIT(4)446 #define Cmd9346CR_9356SEL BIT(4)450 #define GPIOSEL_ENBT BIT(5)457 /* GPIO pins output enable when a bit is set to "1"; otherwise,464 #define HSIMR_GPIO12_0_INT_EN BIT(0)465 #define HSIMR_SPS_OCP_INT_EN BIT(5)466 #define HSIMR_RON_INT_EN BIT(6)467 #define HSIMR_PDN_INT_EN BIT(7)[all …]
48 #define HWMON_C_TEMP_RESET_HISTORY BIT(hwmon_chip_temp_reset_history)49 #define HWMON_C_IN_RESET_HISTORY BIT(hwmon_chip_in_reset_history)50 #define HWMON_C_CURR_RESET_HISTORY BIT(hwmon_chip_curr_reset_history)51 #define HWMON_C_POWER_RESET_HISTORY BIT(hwmon_chip_power_reset_history)52 #define HWMON_C_REGISTER_TZ BIT(hwmon_chip_register_tz)53 #define HWMON_C_UPDATE_INTERVAL BIT(hwmon_chip_update_interval)54 #define HWMON_C_ALARMS BIT(hwmon_chip_alarms)55 #define HWMON_C_SAMPLES BIT(hwmon_chip_samples)56 #define HWMON_C_CURR_SAMPLES BIT(hwmon_chip_curr_samples)57 #define HWMON_C_IN_SAMPLES BIT(hwmon_chip_in_samples)[all …]
7 #define DE_STATE1_DE_ABORT BIT(0)10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)20 #define SYSTEM_CTRL_PCI_BURST BIT(29)21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)[all …]
302 #define RXDMA_AGG_EN BIT(7)306 /* Regsiter Bit and Content definition */308 #define ISO_MD2PP BIT(0)309 #define ISO_PA2PCIE BIT(3)310 #define ISO_PLL2MD BIT(4)311 #define ISO_PWC_DV2RP BIT(11)312 #define ISO_PWC_RV2RP BIT(12)315 #define FEN_MREGEN BIT(15)316 #define FEN_DCORE BIT(11)317 #define FEN_CPUEN BIT(10)[all …]
18 #define RDES0_PAYLOAD_CSUM_ERR BIT(0)19 #define RDES0_CRC_ERROR BIT(1)20 #define RDES0_DRIBBLING BIT(2)21 #define RDES0_MII_ERROR BIT(3)22 #define RDES0_RECEIVE_WATCHDOG BIT(4)23 #define RDES0_FRAME_TYPE BIT(5)24 #define RDES0_COLLISION BIT(6)25 #define RDES0_IPC_CSUM_ERROR BIT(7)26 #define RDES0_LAST_DESCRIPTOR BIT(8)27 #define RDES0_FIRST_DESCRIPTOR BIT(9)[all …]
28 #define XGMAC_CONFIG_JD BIT(16)29 #define XGMAC_CONFIG_TE BIT(0)32 #define XGMAC_CONFIG_ARPEN BIT(31)38 #define XGMAC_CONFIG_S2KP BIT(11)39 #define XGMAC_CONFIG_LM BIT(10)40 #define XGMAC_CONFIG_IPC BIT(9)41 #define XGMAC_CONFIG_JE BIT(8)42 #define XGMAC_CONFIG_WD BIT(7)43 #define XGMAC_CONFIG_GPSLCE BIT(6)44 #define XGMAC_CONFIG_CST BIT(2)[all …]
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)35 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)[all …]
320 #define CMDEEPROM_EN BIT(5)321 #define CMDEEPROM_SEL BIT(4)322 #define CMD9346CR_9356SEL BIT(4)327 #define GPIOSEL_ENBT BIT(5)345 #define RRSR_1M BIT(0)346 #define RRSR_2M BIT(1)347 #define RRSR_5_5M BIT(2)348 #define RRSR_11M BIT(3)349 #define RRSR_6M BIT(4)350 #define RRSR_9M BIT(5)[all …]
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)16 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)17 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)18 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)19 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)34 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)35 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)39 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)40 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)[all …]
