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/Linux-v6.1/lib/
Dbch.c2 * Generic binary BCH encoding/decoding library
24 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
33 * On systems supporting hw BCH features, intermediate results may be provided
40 * (m,t) are fixed and known in advance, e.g. when using BCH error correction
75 #include <linux/bch.h>
152 static u8 swap_bits(struct bch_control *bch, u8 in) in swap_bits() argument
154 if (!bch->swap_bits) in swap_bits()
163 static void bch_encode_unaligned(struct bch_control *bch, in bch_encode_unaligned() argument
169 const int l = BCH_ECC_WORDS(bch)-1; in bch_encode_unaligned()
172 u8 tmp = swap_bits(bch, *data++); in bch_encode_unaligned()
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/Linux-v6.1/drivers/mtd/nand/raw/ingenic/
Djz4725b_bch.c3 * JZ4725B BCH controller driver
59 /* Timeout for BCH calculation/correction. */
62 static inline void jz4725b_bch_config_set(struct ingenic_ecc *bch, u32 cfg) in jz4725b_bch_config_set() argument
64 writel(cfg, bch->base + BCH_BHCSR); in jz4725b_bch_config_set()
67 static inline void jz4725b_bch_config_clear(struct ingenic_ecc *bch, u32 cfg) in jz4725b_bch_config_clear() argument
69 writel(cfg, bch->base + BCH_BHCCR); in jz4725b_bch_config_clear()
72 static int jz4725b_bch_reset(struct ingenic_ecc *bch, in jz4725b_bch_reset() argument
78 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4725b_bch_reset()
80 /* Initialise and enable BCH. */ in jz4725b_bch_reset()
81 jz4725b_bch_config_clear(bch, 0x1f); in jz4725b_bch_reset()
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Djz4780_bch.c3 * JZ4780 BCH controller driver
59 /* Timeout for BCH calculation/correction. */
62 static void jz4780_bch_reset(struct ingenic_ecc *bch, in jz4780_bch_reset() argument
68 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4780_bch_reset()
70 /* Set up BCH count register. */ in jz4780_bch_reset()
73 writel(reg, bch->base + BCH_BHCNT); in jz4780_bch_reset()
75 /* Initialise and enable BCH. */ in jz4780_bch_reset()
80 writel(reg, bch->base + BCH_BHCR); in jz4780_bch_reset()
83 static void jz4780_bch_disable(struct ingenic_ecc *bch) in jz4780_bch_disable() argument
85 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4780_bch_disable()
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DKconfig8 based boards, using the BCH controller for hardware error correction.
16 tristate "Hardware BCH support for JZ4740 SoC"
26 tristate "Hardware BCH support for JZ4725B SoC"
29 Enable this driver to support the BCH error-correction hardware
33 will be called jz4725b-bch.
36 tristate "Hardware BCH support for JZ4780 SoC"
39 Enable this driver to support the BCH error-correction hardware
43 will be called jz4780-bch.
/Linux-v6.1/drivers/isdn/mISDN/
Dhwchannel.c39 struct bchannel *bch = container_of(ws, struct bchannel, workq); in bchannel_bh() local
43 if (test_and_clear_bit(FLG_RECVQUEUE, &bch->Flags)) { in bchannel_bh()
44 while ((skb = skb_dequeue(&bch->rqueue))) { in bchannel_bh()
45 bch->rcount--; in bchannel_bh()
46 if (likely(bch->ch.peer)) { in bchannel_bh()
47 err = bch->ch.recv(bch->ch.peer, skb); in bchannel_bh()
156 mISDN_ctrl_bchannel(struct bchannel *bch, struct mISDN_ctrl_req *cq) in mISDN_ctrl_bchannel() argument
167 memset(bch->fill, cq->p2 & 0xff, MISDN_BCH_FILL_SIZE); in mISDN_ctrl_bchannel()
168 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags); in mISDN_ctrl_bchannel()
170 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); in mISDN_ctrl_bchannel()
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Dl1oip_core.c354 struct bchannel *bch; in l1oip_socket_recv() local
376 bch = hc->chan[channel].bch; in l1oip_socket_recv()
377 if (!dch && !bch) { in l1oip_socket_recv()
405 if (bch) { in l1oip_socket_recv()
435 queue_ch_frame(&bch->ch, PH_DATA_IND, rx_counter, nskb); in l1oip_socket_recv()
1007 struct bchannel *bch; in open_bchannel() local
1015 bch = hc->chan[ch].bch; in open_bchannel()
1016 if (!bch) { in open_bchannel()
1017 printk(KERN_ERR "%s:internal error ch %d has no bch\n", in open_bchannel()
1021 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) in open_bchannel()
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/Linux-v6.1/drivers/isdn/hardware/mISDN/
Davmfritz.c130 struct bchannel bch[2]; member
141 card->bch[0].debug = debug; in _set_debug()
142 card->bch[1].debug = debug; in _set_debug()
250 if (test_bit(FLG_ACTIVE, &fc->bch[0].Flags) && in Sel_BCS()
251 (fc->bch[0].nr & channel)) in Sel_BCS()
252 return &fc->bch[0]; in Sel_BCS()
253 else if (test_bit(FLG_ACTIVE, &fc->bch[1].Flags) && in Sel_BCS()
254 (fc->bch[1].nr & channel)) in Sel_BCS()
255 return &fc->bch[1]; in Sel_BCS()
275 write_ctrl(struct bchannel *bch, int which) { in write_ctrl() argument
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DmISDNisar.c68 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) { in send_mbox()
97 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) { in rcv_mbox()
174 u32 saved_debug = isar->ch[0].bch.debug; in load_firmware()
193 isar->ch[0].bch.debug &= ~DEBUG_HW_BFIFO; in load_firmware()
280 isar->ch[0].bch.debug = saved_debug; in load_firmware()
392 isar->ch[0].bch.debug = saved_debug; in load_firmware()
404 _queue_data(&ch->bch.ch, PH_CONTROL_IND, status, 0, NULL, GFP_ATOMIC); in deliver_status()
418 if (test_bit(FLG_RX_OFF, &ch->bch.Flags)) { in isar_rcv_frame()
419 ch->bch.dropcnt += ch->is->clsb; in isar_rcv_frame()
423 switch (ch->bch.state) { in isar_rcv_frame()
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Dnetjet.c42 struct bchannel bch; member
96 card->bc[0].bch.debug = debug; in _set_debug()
97 card->bc[1].bch.debug = debug; in _set_debug()
177 struct tiger_hw *card = bc->bch.hw; in fill_mem()
181 bc->bch.nr, fill, cnt, idx, card->send.idx); in fill_mem()
182 if (bc->bch.nr & 2) { in fill_mem()
200 struct tiger_hw *card = bc->bch.hw; in mode_tiger()
203 bc->bch.nr, bc->bch.state, protocol); in mode_tiger()
206 if (bc->bch.state == ISDN_P_NONE) in mode_tiger()
209 bc->bch.state = protocol; in mode_tiger()
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Dw6692.c45 struct bchannel bch; member
83 card->bc[0].bch.debug = debug; in _set_debug()
84 card->bc[1].bch.debug = debug; in _set_debug()
447 struct w6692_hw *card = wch->bch.hw; in W6692_empty_Bfifo()
452 if (unlikely(wch->bch.state == ISDN_P_NONE)) { in W6692_empty_Bfifo()
455 if (wch->bch.rx_skb) in W6692_empty_Bfifo()
456 skb_trim(wch->bch.rx_skb, 0); in W6692_empty_Bfifo()
459 if (test_bit(FLG_RX_OFF, &wch->bch.Flags)) { in W6692_empty_Bfifo()
460 wch->bch.dropcnt += count; in W6692_empty_Bfifo()
464 maxlen = bchannel_get_rxbuf(&wch->bch, count); in W6692_empty_Bfifo()
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Dhfcpci.c134 struct bchannel bch[2]; member
309 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) && in Sel_BCS()
310 (hc->bch[0].nr & channel)) in Sel_BCS()
311 return &hc->bch[0]; in Sel_BCS()
312 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) && in Sel_BCS()
313 (hc->bch[1].nr & channel)) in Sel_BCS()
314 return &hc->bch[1]; in Sel_BCS()
367 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL) in hfcpci_clear_fifo_tx()
381 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL) in hfcpci_clear_fifo_tx()
393 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz, in hfcpci_empty_bfifo() argument
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DmISDNipac.c885 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr, in waitforCEC()
888 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr); in waitforCEC()
905 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr, in waitforXFW()
908 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr); in waitforXFW()
928 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count); in hscx_empty_fifo()
929 if (test_bit(FLG_RX_OFF, &hscx->bch.Flags)) { in hscx_empty_fifo()
930 hscx->bch.dropcnt += count; in hscx_empty_fifo()
934 maxlen = bchannel_get_rxbuf(&hscx->bch, count); in hscx_empty_fifo()
937 if (hscx->bch.rx_skb) in hscx_empty_fifo()
938 skb_trim(hscx->bch.rx_skb, 0); in hscx_empty_fifo()
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Dhfcsusb.c47 static int hfcsusb_setup_bch(struct bchannel *bch, int protocol);
48 static void deactivate_bchannel(struct bchannel *bch);
198 struct bchannel *bch = container_of(ch, struct bchannel, ch); in hfcusb_l2l1B() local
199 struct hfcsusb *hw = bch->hw; in hfcusb_l2l1B()
210 ret = bchannel_senddata(bch, skb); in hfcusb_l2l1B()
219 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { in hfcusb_l2l1B()
220 hfcsusb_start_endpoint(hw, bch->nr - 1); in hfcusb_l2l1B()
221 ret = hfcsusb_setup_bch(bch, ch->protocol); in hfcusb_l2l1B()
229 deactivate_bchannel(bch); in hfcusb_l2l1B()
251 phi = kzalloc(struct_size(phi, bch, dch->dev.nrbchan), GFP_ATOMIC); in hfcsusb_ph_info()
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Dhfcmulti.c844 struct bchannel *bch = hc->chan[ch].bch; in vpm_echocan_on() local
852 if (!bch) in vpm_echocan_on()
859 recv_Bchannel_skb(bch, skb); in vpm_echocan_on()
876 struct bchannel *bch = hc->chan[ch].bch; in vpm_echocan_off() local
885 if (!bch) in vpm_echocan_off()
892 recv_Bchannel_skb(bch, skb); in vpm_echocan_off()
1830 struct bchannel *bch = NULL; in hfcmulti_dtmf() local
1842 bch = hc->chan[ch].bch; in hfcmulti_dtmf()
1843 if (!bch) in hfcmulti_dtmf()
1847 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) in hfcmulti_dtmf()
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/Linux-v6.1/drivers/mtd/nand/
Decc-sw-bch.c4 * using binary BCH codes. It relies on the generic BCH library lib/bch.c.
15 #include <linux/mtd/nand-ecc-sw-bch.h>
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
57 count = bch_decode(engine_conf->bch, NULL, step_size, read_ecc, in nand_ecc_sw_bch_correct()
79 * nand_ecc_sw_bch_cleanup - Cleanup software BCH ECC resources
86 bch_free(engine_conf->bch); in nand_ecc_sw_bch_cleanup()
92 * nand_ecc_sw_bch_init - Initialize software BCH ECC engine
95 * Returns: a pointer to a new NAND BCH control structure, or NULL upon failure
97 * Initialize NAND BCH error correction. @nand.ecc parameters 'step_size' and
98 * 'bytes' are used to compute the following BCH parameters:
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DKconfig27 more strength correction and in this case BCH or RS will be
39 bool "Software BCH ECC engine"
40 select BCH
44 This enables support for software BCH error correction. Binary BCH
/Linux-v6.1/drivers/md/bcache/
Dfeatures.h40 BCH##_FEATURE_COMPAT_##flagname) != 0); \
45 BCH##_FEATURE_COMPAT_##flagname; \
50 ~BCH##_FEATURE_COMPAT_##flagname; \
59 BCH##_FEATURE_RO_COMPAT_##flagname) != 0); \
64 BCH##_FEATURE_RO_COMPAT_##flagname; \
69 ~BCH##_FEATURE_RO_COMPAT_##flagname; \
78 BCH##_FEATURE_INCOMPAT_##flagname) != 0); \
83 BCH##_FEATURE_INCOMPAT_##flagname; \
88 ~BCH##_FEATURE_INCOMPAT_##flagname; \
/Linux-v6.1/Documentation/devicetree/bindings/mtd/
Dgpmi-nand.yaml36 - description: Address and length of bch block.
41 - const: bch
47 const: bch
127 - description: SoC gpmi bch clock
128 - description: SoC gpmi bch apb clock
129 - description: SoC per1 bch clock
148 - description: SoC gpmi bch apb clock
161 reg-names = "gpmi-nand", "bch";
163 interrupt-names = "bch";
Dnvidia-tegra20-nand.txt28 Supported values with "hw" ECC mode are: "rs", "bch".
35 - BCH: 4, 8, 14, 16
60 nand-ecc-algo = "bch";
Dmtk-nand.txt36 ecc-engine = <&bch>;
158 Required BCH properties:
170 bch: ecc@1100e000 {
/Linux-v6.1/include/linux/mtd/
Dnand-ecc-sw-bch.h5 * This file is the header for the NAND BCH ECC implementation.
12 #include <linux/bch.h>
15 * struct nand_ecc_sw_bch_conf - private software BCH ECC engine structure
21 * @bch: BCH control structure
30 struct bch_control *bch; member
/Linux-v6.1/include/linux/
Dbch.h3 * Generic binary BCH encoding/decoding library
12 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
20 * struct bch_control - BCH control structure
61 void bch_free(struct bch_control *bch);
63 void bch_encode(struct bch_control *bch, const uint8_t *data,
66 int bch_decode(struct bch_control *bch, const uint8_t *data, unsigned int len,
/Linux-v6.1/drivers/mtd/nand/raw/gpmi-nand/
Dgpmi-nand.c21 #include "bch-regs.h"
25 #define GPMI_NAND_BCH_REGS_ADDR_RES_NAME "bch"
26 #define GPMI_NAND_BCH_INTERRUPT_RES_NAME "bch"
66 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
67 * If you try to soft reset the BCH block, it becomes unusable until
69 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
70 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
162 * Reset BCH here, too. We got failures otherwise :( in gpmi_init()
163 * See later BCH reset for explanation of MX23 and MX28 handling in gpmi_init()
179 /* Select BCH ECC. */ in gpmi_init()
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Dgpmi-nand.h26 * struct bch_geometry - BCH geometry description.
132 /* BCH */
147 bool bch; member
164 /* BCH : Status Block Completion Codes */
/Linux-v6.1/drivers/mtd/devices/
Ddocg3.c21 #include <linux/bch.h>
41 * - a 7 bytes BCH code stored in the OOB for each page
42 * The BCH ECC is :
43 * - BCH is in GF(2^14)
44 * - BCH is over data of 520 bytes (512 page + 7 page_info bytes
46 * - BCH can correct up to 4 bits (t = 4)
47 * - BCH syndroms are calculated in hardware, and checked in hardware as well
62 /* byte 7 is Hamming ECC, byte 8-14 are BCH ECC */ in docg3_ooblayout_ecc()
550 * @len: the number of bytes covered by the ECC (BCH covered)
553 * ECC (on 1 byte) and the BCH hardware ECC (on 7 bytes).
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