Home
last modified time | relevance | path

Searched full:bch (Results 1 – 25 of 99) sorted by relevance

1234

/Linux-v5.4/lib/
Dbch.c2 * Generic binary BCH encoding/decoding library
24 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
33 * On systems supporting hw BCH features, intermediate results may be provided
40 * (m,t) are fixed and known in advance, e.g. when using BCH error correction
75 #include <linux/bch.h>
120 static void encode_bch_unaligned(struct bch_control *bch, in encode_bch_unaligned() argument
126 const int l = BCH_ECC_WORDS(bch)-1; in encode_bch_unaligned()
129 p = bch->mod8_tab + (l+1)*(((ecc[0] >> 24)^(*data++)) & 0xff); in encode_bch_unaligned()
141 static void load_ecc8(struct bch_control *bch, uint32_t *dst, in load_ecc8() argument
145 unsigned int i, nwords = BCH_ECC_WORDS(bch)-1; in load_ecc8()
[all …]
/Linux-v5.4/drivers/mtd/nand/raw/ingenic/
Djz4725b_bch.c3 * JZ4725B BCH controller driver
59 /* Timeout for BCH calculation/correction. */
62 static inline void jz4725b_bch_config_set(struct ingenic_ecc *bch, u32 cfg) in jz4725b_bch_config_set() argument
64 writel(cfg, bch->base + BCH_BHCSR); in jz4725b_bch_config_set()
67 static inline void jz4725b_bch_config_clear(struct ingenic_ecc *bch, u32 cfg) in jz4725b_bch_config_clear() argument
69 writel(cfg, bch->base + BCH_BHCCR); in jz4725b_bch_config_clear()
72 static int jz4725b_bch_reset(struct ingenic_ecc *bch, in jz4725b_bch_reset() argument
78 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4725b_bch_reset()
80 /* Initialise and enable BCH. */ in jz4725b_bch_reset()
81 jz4725b_bch_config_clear(bch, 0x1f); in jz4725b_bch_reset()
[all …]
Djz4780_bch.c3 * JZ4780 BCH controller driver
59 /* Timeout for BCH calculation/correction. */
62 static void jz4780_bch_reset(struct ingenic_ecc *bch, in jz4780_bch_reset() argument
68 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4780_bch_reset()
70 /* Set up BCH count register. */ in jz4780_bch_reset()
73 writel(reg, bch->base + BCH_BHCNT); in jz4780_bch_reset()
75 /* Initialise and enable BCH. */ in jz4780_bch_reset()
80 writel(reg, bch->base + BCH_BHCR); in jz4780_bch_reset()
83 static void jz4780_bch_disable(struct ingenic_ecc *bch) in jz4780_bch_disable() argument
85 writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT); in jz4780_bch_disable()
[all …]
DKconfig7 based boards, using the BCH controller for hardware error correction.
15 tristate "Hardware BCH support for JZ4740 SoC"
25 tristate "Hardware BCH support for JZ4725B SoC"
28 Enable this driver to support the BCH error-correction hardware
32 will be called jz4725b-bch.
35 tristate "Hardware BCH support for JZ4780 SoC"
38 Enable this driver to support the BCH error-correction hardware
42 will be called jz4780-bch.
/Linux-v5.4/drivers/isdn/mISDN/
Dhwchannel.c39 struct bchannel *bch = container_of(ws, struct bchannel, workq); in bchannel_bh() local
43 if (test_and_clear_bit(FLG_RECVQUEUE, &bch->Flags)) { in bchannel_bh()
44 while ((skb = skb_dequeue(&bch->rqueue))) { in bchannel_bh()
45 bch->rcount--; in bchannel_bh()
46 if (likely(bch->ch.peer)) { in bchannel_bh()
47 err = bch->ch.recv(bch->ch.peer, skb); in bchannel_bh()
156 mISDN_ctrl_bchannel(struct bchannel *bch, struct mISDN_ctrl_req *cq) in mISDN_ctrl_bchannel() argument
167 memset(bch->fill, cq->p2 & 0xff, MISDN_BCH_FILL_SIZE); in mISDN_ctrl_bchannel()
168 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags); in mISDN_ctrl_bchannel()
170 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); in mISDN_ctrl_bchannel()
[all …]
Dl1oip_core.c354 struct bchannel *bch; in l1oip_socket_recv() local
376 bch = hc->chan[channel].bch; in l1oip_socket_recv()
377 if (!dch && !bch) { in l1oip_socket_recv()
405 if (bch) { in l1oip_socket_recv()
435 queue_ch_frame(&bch->ch, PH_DATA_IND, rx_counter, nskb); in l1oip_socket_recv()
1005 struct bchannel *bch; in open_bchannel() local
1013 bch = hc->chan[ch].bch; in open_bchannel()
1014 if (!bch) { in open_bchannel()
1015 printk(KERN_ERR "%s:internal error ch %d has no bch\n", in open_bchannel()
1019 if (test_and_set_bit(FLG_OPEN, &bch->Flags)) in open_bchannel()
[all …]
/Linux-v5.4/drivers/isdn/hardware/mISDN/
Davmfritz.c130 struct bchannel bch[2]; member
141 card->bch[0].debug = debug; in _set_debug()
142 card->bch[1].debug = debug; in _set_debug()
250 if (test_bit(FLG_ACTIVE, &fc->bch[0].Flags) && in Sel_BCS()
251 (fc->bch[0].nr & channel)) in Sel_BCS()
252 return &fc->bch[0]; in Sel_BCS()
253 else if (test_bit(FLG_ACTIVE, &fc->bch[1].Flags) && in Sel_BCS()
254 (fc->bch[1].nr & channel)) in Sel_BCS()
255 return &fc->bch[1]; in Sel_BCS()
275 write_ctrl(struct bchannel *bch, int which) { in write_ctrl() argument
[all …]
DmISDNisar.c69 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) { in send_mbox()
98 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) { in rcv_mbox()
175 u32 saved_debug = isar->ch[0].bch.debug; in load_firmware()
194 isar->ch[0].bch.debug &= ~DEBUG_HW_BFIFO; in load_firmware()
281 isar->ch[0].bch.debug = saved_debug; in load_firmware()
393 isar->ch[0].bch.debug = saved_debug; in load_firmware()
405 _queue_data(&ch->bch.ch, PH_CONTROL_IND, status, 0, NULL, GFP_ATOMIC); in deliver_status()
419 if (test_bit(FLG_RX_OFF, &ch->bch.Flags)) { in isar_rcv_frame()
420 ch->bch.dropcnt += ch->is->clsb; in isar_rcv_frame()
424 switch (ch->bch.state) { in isar_rcv_frame()
[all …]
Dnetjet.c42 struct bchannel bch; member
96 card->bc[0].bch.debug = debug; in _set_debug()
97 card->bc[1].bch.debug = debug; in _set_debug()
177 struct tiger_hw *card = bc->bch.hw; in fill_mem()
181 bc->bch.nr, fill, cnt, idx, card->send.idx); in fill_mem()
182 if (bc->bch.nr & 2) { in fill_mem()
200 struct tiger_hw *card = bc->bch.hw; in mode_tiger()
203 bc->bch.nr, bc->bch.state, protocol); in mode_tiger()
206 if (bc->bch.state == ISDN_P_NONE) in mode_tiger()
209 bc->bch.state = protocol; in mode_tiger()
[all …]
Dw6692.c45 struct bchannel bch; member
83 card->bc[0].bch.debug = debug; in _set_debug()
84 card->bc[1].bch.debug = debug; in _set_debug()
447 struct w6692_hw *card = wch->bch.hw; in W6692_empty_Bfifo()
452 if (unlikely(wch->bch.state == ISDN_P_NONE)) { in W6692_empty_Bfifo()
455 if (wch->bch.rx_skb) in W6692_empty_Bfifo()
456 skb_trim(wch->bch.rx_skb, 0); in W6692_empty_Bfifo()
459 if (test_bit(FLG_RX_OFF, &wch->bch.Flags)) { in W6692_empty_Bfifo()
460 wch->bch.dropcnt += count; in W6692_empty_Bfifo()
464 maxlen = bchannel_get_rxbuf(&wch->bch, count); in W6692_empty_Bfifo()
[all …]
Dhfcpci.c134 struct bchannel bch[2]; member
308 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) && in Sel_BCS()
309 (hc->bch[0].nr & channel)) in Sel_BCS()
310 return &hc->bch[0]; in Sel_BCS()
311 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) && in Sel_BCS()
312 (hc->bch[1].nr & channel)) in Sel_BCS()
313 return &hc->bch[1]; in Sel_BCS()
366 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL) in hfcpci_clear_fifo_tx()
380 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL) in hfcpci_clear_fifo_tx()
392 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz, in hfcpci_empty_bfifo() argument
[all …]
DmISDNipac.c885 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr, in waitforCEC()
888 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr); in waitforCEC()
905 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr, in waitforXFW()
908 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr); in waitforXFW()
928 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count); in hscx_empty_fifo()
929 if (test_bit(FLG_RX_OFF, &hscx->bch.Flags)) { in hscx_empty_fifo()
930 hscx->bch.dropcnt += count; in hscx_empty_fifo()
934 maxlen = bchannel_get_rxbuf(&hscx->bch, count); in hscx_empty_fifo()
937 if (hscx->bch.rx_skb) in hscx_empty_fifo()
938 skb_trim(hscx->bch.rx_skb, 0); in hscx_empty_fifo()
[all …]
Dhfcsusb.c47 static int hfcsusb_setup_bch(struct bchannel *bch, int protocol);
48 static void deactivate_bchannel(struct bchannel *bch);
198 struct bchannel *bch = container_of(ch, struct bchannel, ch); in hfcusb_l2l1B() local
199 struct hfcsusb *hw = bch->hw; in hfcusb_l2l1B()
210 ret = bchannel_senddata(bch, skb); in hfcusb_l2l1B()
219 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { in hfcusb_l2l1B()
220 hfcsusb_start_endpoint(hw, bch->nr - 1); in hfcusb_l2l1B()
221 ret = hfcsusb_setup_bch(bch, ch->protocol); in hfcusb_l2l1B()
229 deactivate_bchannel(bch); in hfcusb_l2l1B()
251 phi = kzalloc(struct_size(phi, bch, dch->dev.nrbchan), GFP_ATOMIC); in hfcsusb_ph_info()
[all …]
Dhfcmulti.c844 struct bchannel *bch = hc->chan[ch].bch; in vpm_echocan_on() local
852 if (!bch) in vpm_echocan_on()
859 recv_Bchannel_skb(bch, skb); in vpm_echocan_on()
876 struct bchannel *bch = hc->chan[ch].bch; in vpm_echocan_off() local
885 if (!bch) in vpm_echocan_off()
892 recv_Bchannel_skb(bch, skb); in vpm_echocan_off()
1830 struct bchannel *bch = NULL; in hfcmulti_dtmf() local
1842 bch = hc->chan[ch].bch; in hfcmulti_dtmf()
1843 if (!bch) in hfcmulti_dtmf()
1847 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) in hfcmulti_dtmf()
[all …]
/Linux-v5.4/drivers/mtd/nand/raw/
Dnand_bch.c4 * using binary BCH codes. It relies on the generic BCH library lib/bch.c.
17 #include <linux/bch.h>
20 * struct nand_bch_control - private NAND BCH control structure
21 * @bch: BCH control structure
26 struct bch_control *bch; member
44 encode_bch(nbc->bch, buf, chip->ecc.size, code); in nand_bch_calculate_ecc()
70 count = decode_bch(nbc->bch, NULL, chip->ecc.size, read_ecc, calc_ecc, in nand_bch_correct_data()
91 * nand_bch_init - [NAND Interface] Initialize NAND BCH error correction
95 * a pointer to a new NAND BCH control structure, or NULL upon failure
97 * Initialize NAND BCH error correction. Parameters @eccsize and @eccbytes
[all …]
DKconfig26 bool "Support software BCH ECC"
27 select BCH
30 This enables support for software BCH error correction. Binary BCH
73 bool "Support hardware based BCH error correction"
75 select BCH
78 locate and correct errors when using BCH ECC scheme. This offloads
271 The GPMI controller is very powerful, with the help of BCH
/Linux-v5.4/include/linux/
Dbch.h3 * Generic binary BCH encoding/decoding library
12 * Bose-Chaudhuri-Hocquenghem (BCH) codes.
20 * struct bch_control - BCH control structure
58 void free_bch(struct bch_control *bch);
60 void encode_bch(struct bch_control *bch, const uint8_t *data,
63 int decode_bch(struct bch_control *bch, const uint8_t *data, unsigned int len,
/Linux-v5.4/Documentation/devicetree/bindings/mtd/
Dgpmi-nand.txt13 - reg : should contain registers location and length for gpmi and bch.
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
15 - interrupts : BCH interrupt number.
16 - interrupt-names : Should be "bch".
66 reg-names = "gpmi-nand", "bch";
68 interrupt-names = "bch";
Dingenic,jz4780-nand.txt51 ecc-engine = <&bch>;
80 * ingenic,jz4725b-bch
81 * ingenic,jz4780-bch
87 bch: bch@134d0000 {
88 compatible = "ingenic,jz4780-bch";
Dnvidia-tegra20-nand.txt28 Supported values with "hw" ECC mode are: "rs", "bch".
35 - BCH: 4, 8, 14, 16
60 nand-ecc-algo = "bch";
/Linux-v5.4/include/linux/mtd/
Dnand_bch.h5 * This file is the header for the NAND BCH ECC implementation.
20 * Calculate BCH ecc code
31 * Initialize BCH encoder/decoder
35 * Release BCH encoder/decoder resources
/Linux-v5.4/drivers/mtd/nand/raw/gpmi-nand/
Dgpmi-nand.c21 #include "bch-regs.h"
25 #define GPMI_NAND_BCH_REGS_ADDR_RES_NAME "bch"
26 #define GPMI_NAND_BCH_INTERRUPT_RES_NAME "bch"
66 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
67 * If you try to soft reset the BCH block, it becomes unusable until
69 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
70 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
156 * Reset BCH here, too. We got failures otherwise :( in gpmi_init()
157 * See later BCH reset for explanation of MX23 and MX28 handling in gpmi_init()
173 /* Select BCH ECC. */ in gpmi_init()
[all …]
Dgpmi-nand.h26 * struct bch_geometry - BCH geometry description.
128 /* BCH */
143 bool bch; member
160 /* BCH : Status Block Completion Codes */
/Linux-v5.4/drivers/mtd/devices/
Ddocg3.c21 #include <linux/bch.h>
41 * - a 7 bytes BCH code stored in the OOB for each page
42 * The BCH ECC is :
43 * - BCH is in GF(2^14)
44 * - BCH is over data of 520 bytes (512 page + 7 page_info bytes
46 * - BCH can correct up to 4 bits (t = 4)
47 * - BCH syndroms are calculated in hardware, and checked in hardware as well
62 /* byte 7 is Hamming ECC, byte 8-14 are BCH ECC */ in docg3_ooblayout_ecc()
550 * @len: the number of bytes covered by the ECC (BCH covered)
553 * ECC (on 1 byte) and the BCH hardware ECC (on 7 bytes).
[all …]
/Linux-v5.4/arch/mips/boot/dts/ingenic/
Dci20.dts100 ingenic,bch-controller = <&bch>;
183 &bch {

1234