| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelakex/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
9 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
15 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
35 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
50 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
65 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
116 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
125 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/icelake/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
9 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
15 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
23 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
29 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
35 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
50 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
65 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
116 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
125 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/tigerlake/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
9 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
14 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
22 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
27 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
33 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
47 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
62 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
113 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
122 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | frontend.json | 9 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
26 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
32 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou…
47 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
62 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
113 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
122 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
128 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
137 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
143 …fter an interval where the front-end delivered no uops for a period of 16 cycles which was not int…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/goldmont/ |
| D | pipeline.json | 263 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.…
273 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r…
352 "BriefDescription": "Self-Modifying Code detected",
357 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) …
362 "BriefDescription": "Uops issued to the back end per cycle",
367 …end and allocated into the back end of the machine. This event counts uops that retire as well as…
371 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
376 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
407 …ued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uop…
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
8 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
109 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylake/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
8 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
109 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
8 …"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch…
13 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
18 …e Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Strea…
23 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
28 …-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of th…
41 …Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
55 …e stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to th…
101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
109 …r an interval where the front-end delivered no uops for a period of at least 1 cycle which was not…
[all …]
|
| /Linux-v6.1/fs/erofs/ |
| D | namei.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017-2018 HUAWEI, Inc.
13 const unsigned char *end; member
16 /* based on the end of qn is accurate and it must have the trailing '\0' */
24 * on-disk error, let's only BUG_ON in the debugging mode. in erofs_dirnamecmp()
28 DBG_BUGON(qd->name > qd->end); in erofs_dirnamecmp()
31 /* However it is absolutely safe if < qd->end */ in erofs_dirnamecmp()
32 while (qd->name + i < qd->end && qd->name[i] != '\0') { in erofs_dirnamecmp()
33 if (qn->name[i] != qd->name[i]) { in erofs_dirnamecmp()
35 return qn->name[i] > qd->name[i] ? 1 : -1; in erofs_dirnamecmp()
[all …]
|
| /Linux-v6.1/drivers/media/i2c/ |
| D | ccs-pll.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
56 * A single branch back-end of the CCS PLL tree.
71 * struct ccs_pll - Full CCS PLL configuration
78 * @csi2: CSI-2 related parameters
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| D | pipeline.json | 284 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature",
312 …ocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g.…
324 …ource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), r…
419 …r of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Store…
424 "BriefDescription": "Self-Modifying Code detected",
431 …ction and has to perform a machine clear because of that modification. Self-modifying code (SMC) …
436 "BriefDescription": "Uops issued to the back end per cycle",
443 …end and allocated into the back end of the machine. This event counts uops that retire as well as…
447 "BriefDescription": "Uops requested but not-delivered to the back-end per cycle",
454 …-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and…
[all …]
|
| /Linux-v6.1/sound/soc/fsl/ |
| D | fsl_asrc_dma.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
11 #include <linux/dma/imx-dma.h>
37 chan->private = param; in filter()
45 struct snd_pcm_runtime *runtime = substream->runtime; in fsl_asrc_dma_complete()
46 struct fsl_asrc_pair *pair = runtime->private_data; in fsl_asrc_dma_complete()
48 pair->pos += snd_pcm_lib_period_bytes(substream); in fsl_asrc_dma_complete()
49 if (pair->pos >= snd_pcm_lib_buffer_bytes(substream)) in fsl_asrc_dma_complete()
50 pair->pos = 0; in fsl_asrc_dma_complete()
58 u8 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? OUT : IN; in fsl_asrc_dma_prepare_and_submit()
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/alderlake/ |
| D | frontend.json | 63 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
150 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
165 …fter an interval where the front-end delivered no uops for a period of 128 cycles which was not in…
180 …fter an interval where the front-end delivered no uops for a period of 16 cycles which was not int…
195 "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
210 …fter an interval where the front-end delivered no uops for a period of 256 cycles which was not in…
225 … an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not…
240 …fter an interval where the front-end delivered no uops for a period of 32 cycles which was not int…
255 …after an interval where the front-end delivered no uops for a period of 4 cycles which was not int…
270 …fter an interval where the front-end delivered no uops for a period of 512 cycles which was not in…
[all …]
|
| /Linux-v6.1/arch/sh/mm/ |
| D | cache-sh2a.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh2a.c
47 * Write back the dirty D-caches, but not invalidate them.
53 unsigned long begin, end; in sh2a__flush_wback_region() local
57 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
58 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh2a__flush_wback_region()
59 & ~(L1_CACHE_BYTES-1); in sh2a__flush_wback_region()
66 if (((end - begin) >> PAGE_SHIFT) >= MAX_OCACHE_PAGES) { in sh2a__flush_wback_region()
68 end = begin + (nr_ways * current_cpu_data.dcache.way_size); in sh2a__flush_wback_region()
70 for (v = begin; v < end; v += L1_CACHE_BYTES) { in sh2a__flush_wback_region()
[all …]
|
| D | flush-sh4.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Write back the dirty D-caches, but not invalidate them.
16 reg_size_t aligned_start, v, cnt, end; in sh4__flush_wback_region() local
19 v = aligned_start & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region()
20 end = (aligned_start + size + L1_CACHE_BYTES-1) in sh4__flush_wback_region()
21 & ~(L1_CACHE_BYTES-1); in sh4__flush_wback_region()
22 cnt = (end - v) / L1_CACHE_BYTES; in sh4__flush_wback_region()
33 cnt -= 8; in sh4__flush_wback_region()
38 cnt--; in sh4__flush_wback_region()
43 * Write back the dirty D-caches and invalidate them.
[all …]
|
| D | cache-sh3.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/sh/mm/cache-sh3.c
23 * Write back the dirty D-caches, but not invalidate them.
35 unsigned long begin, end; in sh3__flush_wback_region() local
38 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1); in sh3__flush_wback_region()
39 end = ((unsigned long)start + size + L1_CACHE_BYTES-1) in sh3__flush_wback_region()
40 & ~(L1_CACHE_BYTES-1); in sh3__flush_wback_region()
42 for (v = begin; v < end; v+=L1_CACHE_BYTES) { in sh3__flush_wback_region()
66 * Write back the dirty D-caches and invalidate them.
74 unsigned long begin, end; in sh3__flush_purge_region() local
[all …]
|
| D | cache-sh4.c | 2 * arch/sh/mm/cache-sh4.c
5 * Copyright (C) 2001 - 2009 Paul Mundt
35 * Write back the range of D-cache, and purge the I-cache.
43 unsigned long start, end; in sh4_flush_icache_range() local
47 start = data->addr1; in sh4_flush_icache_range()
48 end = data->addr2; in sh4_flush_icache_range()
51 if (((end - start) >> PAGE_SHIFT) >= MAX_ICACHE_PAGES) { in sh4_flush_icache_range()
57 * Selectively flush d-cache then invalidate the i-cache. in sh4_flush_icache_range()
60 start &= ~(L1_CACHE_BYTES-1); in sh4_flush_icache_range()
61 end += L1_CACHE_BYTES-1; in sh4_flush_icache_range()
[all …]
|
| /Linux-v6.1/lib/lz4/ |
| D | lz4hc_compress.c | 2 * LZ4 HC - High Compression Mode of LZ4
3 * Copyright (C) 2011-2015, Yann Collet.
5 * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php)
27 * - LZ4 homepage : http://www.lz4.org
28 * - LZ4 source repository : https://github.com/lz4/lz4
31 * Sven Schmidt <4sschmid@informatik.uni-hamburg.de>
34 /*-************************************
47 #define OPTIMAL_ML (int)((ML_MASK - 1) + MINMATCH)
50 >> ((MINMATCH*8) - LZ4HC_HASH_LOG))
63 memset((void *)hc4->hashTable, 0, sizeof(hc4->hashTable)); in LZ4HC_init()
[all …]
|
| /Linux-v6.1/arch/arm/mm/ |
| D | cache-fa.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-fa.S
6 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
8 * Based on cache-v4wb.S:
9 * Copyright (C) 1997-2002 Russell king
19 #include "proc-macros.S"
75 * flush_user_cache_range(start, end, flags)
80 * - start - start address (inclusive, page aligned)
81 * - end - end address (exclusive, page aligned)
82 * - flags - vma_area_struct flags describing address space
[all …]
|
| D | cache-v4wb.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v4wb.S
5 * Copyright (C) 1997-2002 Russell king
12 #include "proc-macros.S"
39 * 32768 150 149 150 214 216 212 <---
42 * Whole 132 136 132 221 217 207 <---
89 add r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE
99 * flush_user_cache_range(start, end, flags)
104 * - start - start address (inclusive, page aligned)
105 * - end - end address (exclusive, page aligned)
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | pipeline.json | 108 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
117 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
127 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
137 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
147 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
157 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
207 … For instructions that consist of multiple micro-ops, this event counts exactly once, as the last …
216 … For instructions that consist of multiple micro-ops, this event counts the retirement of the last…
224 …end of the machine is notified that it must restart, so no more instructions will be decoded from …
229 "BriefDescription": "Self-Modifying Code detected",
[all …]
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
26 …back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycl…
179 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca…
248 …back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can b…
274 "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
295 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
305 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
| /Linux-v6.1/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | frontend.json | 3 …t end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected …
12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
26 …back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycl…
179 …-end in delivering uops. Microcode assists are used for complex instructions or scenarios that ca…
248 …back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can b…
274 "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.",
295 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
305 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
|
| /Linux-v6.1/include/linux/ |
| D | pstore_zone.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * struct pstore_zone_info - pstore/zone back-end driver structure
14 * @owner: Module which is responsible for this back-end driver.
15 * @name: Name of the back-end driver.
29 * -EBUSY means try to write again later.
30 * -ENOMSG means to try next zone.
39 * excluding -ENOMSG mean error. -ENOMSG means to try next zone.
|
| /Linux-v6.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| D | hardwaremanager.h | 113 …PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC S…
115 …tStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
116 …rVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
142 …PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write del…
158 PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
159 PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */
160 PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */
161 PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
162 …PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end suppor…
163 …PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end suppor…
[all …]
|
