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/Linux-v5.10/Documentation/vm/
Dtranshuge.rst66 pmd_offset. It's trivial to make the code transparent hugepage aware
71 hugepage aware.
79 Example to make mremap.c transparent hugepage aware with a one liner
93 Locking in hugepage aware code
96 We want as much code as possible hugepage aware, as calling
99 To make pagetable walks huge pmd aware, all you need to do is to call
/Linux-v5.10/Documentation/driver-api/usb/
Ddma.rst14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
25 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
/Linux-v5.10/tools/testing/selftests/drivers/net/mlxsw/
Dextack.sh119 # Test with VLAN-aware bridge.
151 # Only one VLAN-aware bridge is supported, so this should fail with
157 log_test "extack - multiple VLAN-aware bridges creation"
Dvxlan.sh91 log_test "vxlan device with a vlan-aware bridge"
853 log_test "vlan-aware - enslavement to vlan-aware bridge"
862 log_test "vlan-aware - two vnis mapped to the same vlan"
876 log_test "vlan-aware - failed enslavement to vlan-aware bridge"
882 # (i.e., different TTL) are enslaved to the same VLAN-aware bridge,
897 log_test "vlan-aware - failed enslavement to bridge due to conflict"
909 # Create a simple setup with two VxLAN devices and a single VLAN-aware
952 log_info "vxlan entry offload indication - vlan-aware"
1143 log_info "offload indication - replay & cleanup - vlan aware"
/Linux-v5.10/Documentation/block/
Dqueue-sysfs.rst22 of the RAID volume stripe segment. For a zoned block device, either host-aware
123 "host-aware"), the sum of zones belonging to any of the zone states:
134 "host-aware"), the sum of zones belonging to any of the zone states:
186 "host-aware"), this indicates the total number of zones of the device.
268 "none" for regular block devices and "host-aware" or "host-managed" for zoned
269 block devices. The characteristics of host-aware and host-managed zoned block
Ddata-integrity.rst103 It is completely unreasonable for an application to be aware whether
195 5.2 Integrity-Aware Filesystem
198 A filesystem that is integrity-aware can prepare I/Os with IMD
/Linux-v5.10/Documentation/ABI/testing/
Dsysfs-block262 regular block devices and "host-aware" or "host-managed"
264 host-aware and host-managed zoned block devices are
277 device ("host-aware" or "host-managed" zone model). For regular
285 "host-managed" or "host-aware"), the sum of zones belonging to
294 "host-managed" or "host-aware"), the sum of zones belonging to
306 host-aware or host-managed, chunk_sectors indicates the
/Linux-v5.10/Documentation/scheduler/
Dsched-capacity.rst2 Capacity Aware Scheduling
132 Capacity aware scheduling requires an expression of a task's requirements with
247 This means that while the capacity aware scheduling criteria will be written
251 3. Capacity aware scheduling requirements
268 As stated in 2.2, capacity-aware scheduling requires a frequency-invariant task
276 when the kernel is aware of the switched-to frequency (also employed by
328 5. Capacity aware scheduling implementation
367 Wakeup CPU selection in CFS can be eclipsed by Energy Aware Scheduling
Dsched-energy.rst2 Energy Aware Scheduling
8 Energy Aware Scheduling (or EAS) gives the scheduler the ability to predict
128 4. Energy-Aware task placement
320 Energy Aware Scheduling depends on the CPUs of the system having specific
360 The energy-aware wake-up algorithm has a complexity of:
/Linux-v5.10/arch/powerpc/platforms/83xx/
DKconfig49 Be aware that PCI buses can only function when MDS board is plugged
61 Be aware that PCI initialization is the bootloader's
/Linux-v5.10/include/asm-generic/
Drwonce.h5 * READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some
6 * particular ordering. One way to make the compiler aware of ordering is to
/Linux-v5.10/arch/arm/mach-sa1100/include/mach/
Dirqs.h86 * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically
89 * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
/Linux-v5.10/include/linux/
Dshrinker.h15 /* current node being shrunk (for NUMA aware shrinkers) */
32 /* current memcg being shrunk (for memcg aware shrinkers) */
/Linux-v5.10/Documentation/PCI/
Dpcieaer-howto.rst99 To enable AER aware support requires a software driver to configure
141 AER aware drivers of PCI Express component need change the device
262 Express aware?
266 driver when an error happens. But if the driver is not aware of
/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dsecure.txt5 kernel) are not TrustZone aware and run entirely in either the Normal
7 TrustZone aware and need to be able to determine whether devices are
/Linux-v5.10/drivers/gpu/drm/
Ddrm_self_refresh_helper.c31 * &drm_connector_state.self_refresh_aware to true at runtime if it is SR-aware
47 * connectors must be SR aware and all will enter/exit SR mode at the same time.
49 * If the crtc and connector are SR aware, but the panel connected does not
/Linux-v5.10/Documentation/timers/
Dtimers-howto.rst60 quirks you should be aware of.
71 it is something to be aware of.
/Linux-v5.10/fs/zonefs/
DKconfig8 device (e.g. host-managed or host-aware SMR disk drives) as files.
/Linux-v5.10/Documentation/locking/
Dfutex-requeue-pi.rst53 In order to support PI-aware pthread_condvar's, the kernel needs to
106 to be requeued to a PI-aware futex. The implementation is the
/Linux-v5.10/include/linux/mailbox/
Dzynqmp-ipi-message.h13 * Client is supposed to be aware of this.
/Linux-v5.10/tools/include/linux/
Dcompiler.h160 * READ_ONCE and WRITE_ONCE, but only when the compiler is aware of some
161 * particular ordering. One way to make the compiler aware of ordering is to
/Linux-v5.10/Documentation/admin-guide/
Dabi-testing.rst12 be aware of changes that can occur before these interfaces move to
/Linux-v5.10/drivers/net/caif/
DKconfig29 Be aware that if you enable this then you also need to
/Linux-v5.10/arch/powerpc/boot/
Dcuboot.c3 * Compatibility for old (not device tree aware) U-Boot versions
/Linux-v5.10/Documentation/powerpc/
Dtransactional_memory.rst120 However, basic signal handlers don't need to be aware of transactions
123 Transaction-aware signal handlers can read the transactional register state
198 GDB and ptrace are not currently TM-aware. If one stops during a transaction,

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