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/Linux-v5.15/arch/arm64/boot/dts/realtek/
Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/intel/
Dkeembay-soc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a53";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53";
[all …]
/Linux-v5.15/arch/arm64/boot/dts/amazon/
Dalpine-v2.dtsi4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
[all …]
Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
33 compatible = "fixed-clock";
34 clock-frequency = <24000000>;
35 #clock-cells = <0>;
[all …]
Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
[all …]
Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/net/nfc/
Dnfcmrvl.txt4 - compatible: Should be:
5 - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices
6 - "marvell,nfc-i2c" for I2C devices
7 - "marvell,nfc-spi" for SPI devices
10 - pinctrl-names: Contains only one value - "default".
11 - pintctrl-0: Specifies the pin control groups used for this controller.
12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
[all …]
/Linux-v5.15/arch/arm64/boot/dts/rockchip/
Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/arm/
Dapple.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/apple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple ARM Machine Device Tree Bindings
10 - Hector Martin <marcan@marcan.st>
13 ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
18 - Mac mini (M1, 2020)
19 - MacBook Pro (13-inch, M1, 2020)
20 - MacBook Air (M1, 2020)
[all …]
Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
32 are implementation defined, except when the CTI is connected to an ARM v8
35 In this case the ARM v8 architecture defines the required signal connections
38 indicate this feature (arm,coresight-cti-v8-arch).
53 constants defined in <dt-bindings/arm/coresight-cti-dt.h>
60 Note that some hardware trigger signals can be connected to non-CoreSight
[all …]
/Linux-v5.15/drivers/iommu/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += amd/ intel/ arm/
3 obj-$(CONFIG_IOMMU_API) += iommu.o
4 obj-$(CONFIG_IOMMU_API) += iommu-traces.o
5 obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
6 obj-$(CONFIG_IOMMU_DEBUGFS) += iommu-debugfs.o
7 obj-$(CONFIG_IOMMU_DMA) += dma-iommu.o
8 obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o
9 obj-$(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) += io-pgtable-arm-v7s.o
10 obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o
[all …]
/Linux-v5.15/arch/arm64/boot/dts/bitmain/
Dbm1880.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/bm1880-clock.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/bitmain,bm1880-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
[all …]
/Linux-v5.15/arch/arm64/boot/dts/allwinner/
Dsun50i-a100.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-a100-ccu.h>
8 #include <dt-bindings/clock/sun50i-a100-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-a100-ccu.h>
10 #include <dt-bindings/reset/sun50i-a100-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
[all …]
/Linux-v5.15/arch/arm/mm/
Dpmsa-v8.c2 * Based on linux/arch/arm/pmsa-v7.c
4 * ARM PMSAv8 supporting functions.
78 static struct range __initdata io[MPU_MAX_REGIONS]; variable
120 memblock_remove(reg_start, 0 - reg_start); in pmsav8_adjust_lowmem_bounds()
145 return -ENOENT; in __pmsav8_setup_region()
166 return -EINVAL; in pmsav8_setup_ram()
169 lar = (end - 1) & ~(PMSAv8_MINALIGN - 1); in pmsav8_setup_ram()
182 return -EINVAL; in pmsav8_setup_io()
185 lar = (end - 1) & ~(PMSAv8_MINALIGN - 1); in pmsav8_setup_io()
198 return -EINVAL; in pmsav8_setup_fixed()
[all …]
/Linux-v5.15/arch/arm64/kernel/
Dio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Based on arch/arm/kernel/io.c
5 * Copyright (C) 2012 ARM Ltd.
10 #include <linux/io.h>
13 * Copy data from IO memory space to "real" memory space.
21 count--; in __memcpy_fromio()
28 count -= 8; in __memcpy_fromio()
35 count--; in __memcpy_fromio()
41 * Copy data from "real" memory space to IO memory space.
49 count--; in __memcpy_toio()
[all …]
/Linux-v5.15/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
/Linux-v5.15/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/Linux-v5.15/arch/arm/mach-omap1/include/mach/
Dio.h2 * arch/arm/mach-omap1/include/mach/io.h
4 * IO definitions for TI OMAP processors and boards
6 * Copied from arch/arm/mach-sa1100/include/mach/io.h
7 * Copyright (C) 1997-1999 Russell King
30 * 06-12-1997 RMK Created.
31 * 07-04-1999 RMK Major cleanup
/Linux-v5.15/arch/arm/mach-integrator/
Dintegrator_ap.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-integrator/integrator_ap.c
5 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
11 #include <linux/io.h>
31 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
77 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); in irq_resume()
78 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); in irq_resume()
110 u32 phybase = dev->res.start; in integrator_uart_set_mctrl()
162 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
164 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
[all …]

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