Searched full:architecturally (Results 1 – 25 of 63) sorted by relevance
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| /Linux-v5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | instruction.json | 3 …"PublicDescription": "Software increment. Instruction architecturally executed (condition code che…
9 …"PublicDescription": "Instruction architecturally executed. This event counts all retired instruct…
12 "BriefDescription": "Instruction architecturally executed."
17 …"BriefDescription": "Instruction architecturally executed, condition code check pass, exception re…
20 …"PublicDescription": "Instruction architecturally executed, condition code check pass, write to CO…
23 …"BriefDescription": "Instruction architecturally executed, condition code check pass, write to CON…
31 …"PublicDescription": "Instruction architecturally executed, condition code check pass, write to TT…
34 …"BriefDescription": "Instruction architecturally executed, condition code check pass, write to TTB…
37 …"PublicDescription": "Instruction architecturally executed, branch. This event counts all branches…
40 "BriefDescription": "Instruction architecturally executed, branch."
[all …]
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| /Linux-v5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| D | instruction.json | 42 "PublicDescription": "Instruction architecturally executed, software increment",
48 "PublicDescription": "Instruction architecturally executed",
54 …"PublicDescription": "Instruction architecturally executed, condition code check pass, write to CO…
66 … "PublicDescription": "Instruction architecturally executed (condition check pass), write to TTBR",
72 …"PublicDescription": "Instruction architecturally executed, branch. This event counts all branches…
78 …"PublicDescription": "Instruction architecturally executed, mispredicted branch. This event counts…
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| D | exception.json | 45 …"PublicDescription": "Instruction architecturally executed, condition check pass, exception return…
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| /Linux-v5.10/drivers/soc/qcom/ |
| D | kryo-l2-accessors.c | 21 * Use architecturally required barriers for ordering between system register
41 * Use architecturally required barriers for ordering between system register
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| /Linux-v5.10/Documentation/arm64/ |
| D | amu.rst | 27 of four fixed and architecturally defined 64-bit event counters.
32 - Instructions retired: increments with every architecturally executed
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| /Linux-v5.10/arch/arm/include/asm/ |
| D | virt.h | 14 * architecturally defined flag bit here.
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| /Linux-v5.10/arch/x86/include/asm/ |
| D | spec-ctrl.h | 11 * would be easier if SPEC_CTRL were architecturally maskable or
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| D | debugreg.h | 103 dr7 &= ~0x400; /* architecturally set bit */ in local_db_save()
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| /Linux-v5.10/tools/arch/ia64/include/asm/ |
| D | barrier.h | 22 * architecturally visible effects of a memory access have occurred
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| /Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 13 timer interrupt comes from an architecturally mandated real-time timer that is
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| /Linux-v5.10/arch/ia64/include/asm/ |
| D | barrier.h | 20 * architecturally visible effects of a memory access have occurred
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | coresight-cti.yaml | 37 architecturally connected CTI an additional compatible string is used to
235 # v8 architecturally defined CTI - CPU + ETM connections generated by the
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| /Linux-v5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 77 registers, which contain their architecturally-defined reset values. Only
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| D | arm,arch_timer_mmio.yaml | 51 registers, which contain their architecturally-defined reset values. Only
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| /Linux-v5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-mc.yaml | 15 Tegra30 Memory Controller architecturally consists of the following parts:
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| /Linux-v5.10/Documentation/virt/kvm/devices/ |
| D | arm-vgic-v3.rst | 101 architecturally defined behavior to allow software a full view of the
124 The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
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| /Linux-v5.10/Documentation/x86/ |
| D | entry_64.rst | 42 - Architecturally-defined exceptions like divide_error.
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| /Linux-v5.10/drivers/hwtracing/coresight/ |
| D | coresight-cti-platform.c | 17 /* Number of CTI signals in the v8 architecturally defined connection */
170 * Create an architecturally defined v8 connection
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| /Linux-v5.10/arch/parisc/kernel/ |
| D | vmlinux.lds.S | 112 /* Architecturally we need to keep __gp below 0x1000000 and thus
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| /Linux-v5.10/tools/perf/pmu-events/arch/x86/silvermont/ |
| D | pipeline.json | 94 …er of any mispredicted branch instructions retired. This umask is an architecturally defined event…
285 …ate by dividing the event count by the core frequency. This event is architecturally defined and i…
293 …he elapsed time while the core was not in halt state. This event is architecturally defined and i…
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| /Linux-v5.10/arch/arm/vdso/ |
| D | vdsomunge.c | 6 * architecturally specified to be usable by both soft- and hard-float
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| /Linux-v5.10/arch/mips/lib/ |
| D | dump_tlb.c | 134 * We check both G bits, even though architecturally they should in dump_tlb()
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| /Linux-v5.10/arch/arm64/kernel/ |
| D | kaslr.c | 126 * Mix in any entropy obtainable architecturally if enabled in kaslr_early_init()
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| /Linux-v5.10/arch/powerpc/include/uapi/asm/ |
| D | sigcontext.h | 53 * by an additional 32 double words. Architecturally the layout of
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| /Linux-v5.10/arch/mips/kvm/ |
| D | vz.c | 3110 /* architecturally writable (e.g. from guest) */ in kvm_vz_vcpu_setup()
3113 /* architecturally read only, but maybe writable from root */ in kvm_vz_vcpu_setup()
3119 /* architecturally read only, but maybe writable from root */ in kvm_vz_vcpu_setup()
3136 /* architecturally writable (e.g. from guest) */ in kvm_vz_vcpu_setup()
3138 /* architecturally read only, but maybe writable from root */ in kvm_vz_vcpu_setup()
3163 /* architecturally writable (e.g. from guest) */ in kvm_vz_vcpu_setup()
3171 /* architecturally read only, but maybe writable from root */ in kvm_vz_vcpu_setup()
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