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/Linux-v5.10/Documentation/arm64/
Damu.rst9 Date: 2019-09-10
16 ---------------------
24 optional external memory-mapped interface.
27 of four fixed and architecturally defined 64-bit event counters.
29 - CPU cycle counter: increments at the frequency of the CPU.
30 - Constant counter: increments at the fixed frequency of the system
32 - Instructions retired: increments with every architecturally executed
34 - Memory stall cycles: counts instruction dispatch stall cycles caused by
44 64-bit event counters.
50 -------------
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/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dcoresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 number is defined at design time, the maximum of each defined in the DEVID
26 programmable channels, usually 4, but again implementation defined and
32 are implementation defined, except when the CTI is connected to an ARM v8
37 architecturally connected CTI an additional compatible string is used to
38 indicate this feature (arm,coresight-cti-v8-arch).
52 and usages. These can be defined along with the signal indexes with the
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/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree
27 - compatible : "riscv,cpu-intc"
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/Linux-v5.10/arch/arm/include/asm/
Dvirt.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * architecturally defined flag bit here.
24 * A correctly-implemented bootloader must start all CPUs in the same mode:
/Linux-v5.10/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
43 - base field encodes bits [51:16] of the guest physical base address
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/Linux-v5.10/Documentation/devicetree/bindings/timer/
Darm,arch_timer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
17 The per-core architected timer is attached to a GIC to deliver its
18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
24 - items:
25 - enum:
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Darm,arch_timer_mmio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
11 - Mark Rutland <mark.rutland@arm.com>
22 - enum:
23 - arm,armv7-timer-mem
29 '#address-cells':
32 '#size-cells':
37 clock-frequency:
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/Linux-v5.10/arch/parisc/kernel/
Dvmlinux.lds.S1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1999-2003 Matthew Wilcox <willy at parisc-linux.org>
5 * Copyright (C) 2000-2003 Paul Bame <bame at parisc-linux.org>
6 * Copyright (C) 2000 John Marvin <jsm at parisc-linux.org>
8 * Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
9 * Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
10 * Copyright (C) 2006-2013 Helge Deller <deller@gmx.de>
24 #include <asm-generic/vmlinux.lds.h>
29 #include <asm/asm-offsets.h>
34 OUTPUT_FORMAT("elf32-hppa-linux")
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/Linux-v5.10/Documentation/x86/
Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to do_IRQ with
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/Linux-v5.10/drivers/hwtracing/coresight/
Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
17 /* Number of CTI signals in the v8 architecturally defined connection */
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
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/Linux-v5.10/tools/perf/pmu-events/arch/x86/silvermont/
Dpipeline.json94 …architecturally defined event. This event counts the number of retired branch instructions that we…
104 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
114 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
124 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
134 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
144 …he processor predicts that the branch would be taken, but it is not, or vice-versa. When the misp…
153 …"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MS…
159 "BriefDescription": "MSROM micro-ops retired"
162 …-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-op…
168 "BriefDescription": "Micro-ops retired"
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/Linux-v5.10/Documentation/trace/coresight/
Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
11 --------------------
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
47 defined, unless the CPU/ETM combination is a v8 architecture, in which case
48 the connections have an architecturally defined standard layout.
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Dcoresight-etm4x-reference.rst11 ---------------------------
20 ----
37 ----
47 ----
52 - > 0 : Programs up the hardware with the current values held in the driver
55 - = 0 : disable trace hardware.
60 ----
72 ----
85 ----
101 Optional exclude value:-
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/Linux-v5.10/arch/arm64/include/uapi/asm/
Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
62 * Supported CPU Targets - Adding a new target type is not recommended,
127 * Although the control registers are architecturally defined as 32
148 * Architecture specific defines for kvm_guest_debug->control
242 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
251 /* KVM-as-firmware specific pseudo-registers */
263 * - NOT_REQUIRED: the guest doesn't need to do anything
264 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
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/Linux-v5.10/tools/arch/arm64/include/uapi/asm/
Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
62 * Supported CPU Targets - Adding a new target type is not recommended,
127 * Although the control registers are architecturally defined as 32
148 * Architecture specific defines for kvm_guest_debug->control
242 * KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
251 /* KVM-as-firmware specific pseudo-registers */
263 * - NOT_REQUIRED: the guest doesn't need to do anything
264 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
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/Linux-v5.10/drivers/clocksource/
Darc_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
65 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's in arc_read_gfrc()
70 * trying to access two different sub-components (like GFRC, in arc_read_gfrc()
71 * inter-core interrupt, etc...). HW also supports simultaneously in arc_read_gfrc()
75 * defined in arch/arc/kernel/mcip.c in arc_read_gfrc()
110 pr_warn("Global-64-bit-Ctr clocksource not detected\n"); in arc_cs_setup_gfrc()
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/Linux-v5.10/arch/x86/include/asm/
Dmce.h1 /* SPDX-License-Identifier: GPL-2.0 */
46 /* AMD-specific bits */
55 * - Deferred error interrupt type is specifiable by bank.
56 * - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
58 * - TCC bit is present in MCx_STATUS.
66 * bits 15:0. But bit 12 is the 'F' bit, defined for corrected
69 * of uncorrected errors - so the F bit is deliberately skipped
74 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
75 #define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
378 umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; }; in umc_normaddr_to_sysaddr()
/Linux-v5.10/arch/arm64/kvm/
Dreset.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
128 return -EINVAL; in kvm_vcpu_enable_sve()
132 return -EINVAL; in kvm_vcpu_enable_sve()
134 vcpu->arch.sve_max_vl = kvm_sve_max_vl; in kvm_vcpu_enable_sve()
141 vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE; in kvm_vcpu_enable_sve()
148 * vcpu->arch.sve_state as necessary.
155 vl = vcpu->arch.sve_max_vl; in kvm_vcpu_finalize_sve()
160 * set_sve_vls(). Double-check here just to be sure: in kvm_vcpu_finalize_sve()
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/Linux-v5.10/arch/arm64/include/asm/
Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1996-2003 Russell King
53 /* AArch32-specific ptrace requests */
86 #define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */
108 * a syscall -- i.e., its most recent entry into the kernel from
111 * This must have the value -1, for ABI compatibility with ptrace etc.
113 #define NO_SYSCALL (-1)
122 /* Architecturally defined mapping between AArch32 and AArch64 registers */
204 return regs->syscallno != NO_SYSCALL; in in_syscall()
209 regs->syscallno = NO_SYSCALL; in forget_syscall()
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Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
427 * n: 0-15
433 * n: 0-15
441 /* AMU v1: Fixed (architecturally defined) activity monitors */
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/Linux-v5.10/include/asm-generic/
Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
32 * Generic MMU-gather implementation.
49 * - tlb_gather_mmu() / tlb_finish_mmu(); start and finish a mmu_gather
54 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
59 * - tlb_remove_table()
61 * tlb_remove_table() is the basic primitive to free page-table directories
68 * - tlb_remove_page() / __tlb_remove_page()
69 * - tlb_remove_page_size() / __tlb_remove_page_size()
79 * - tlb_change_page_size()
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/Linux-v5.10/arch/arm/probes/
Ddecode.h1 /* SPDX-License-Identifier: GPL-2.0-only */
25 /* str_pc_offset is architecturally defined from ARMv7 onwards */
31 /* We need a run-time check to determine str_pc_offset */
55 it |= it >> (27 - 10); /* Carry ITSTATE<2> to correct place */ in it_advance()
65 long cpsr = regs->ARM_cpsr; in bx_write_pc()
73 regs->ARM_cpsr = cpsr; in bx_write_pc()
74 regs->ARM_pc = pcv; in bx_write_pc()
86 /* We need run-time testing to determine if load_write_pc() should interwork. */
97 regs->ARM_pc = pcv; in load_write_pc()
114 /* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
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/Linux-v5.10/arch/arm64/mm/
Dfault.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 1995-2004 Russell King
19 #include <linux/page-flags.h>
33 #include <asm/debug-monitors.h>
108 return __pa_symbol(mm->pgd); in mm_to_pgd_phys()
110 return (unsigned long)virt_to_phys(mm->pgd); in mm_to_pgd_phys()
124 mm = current->active_mm; in show_pte()
139 pr_alert("%s pgtable: %luk pages, %llu-bit VAs, pgdp=%016lx\n", in show_pte()
188 * like set_pte_at(), the PTE is never changed from no-exec to exec here.
221 /* Invalidate a stale read-only entry */ in ptep_set_access_flags()
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/Linux-v5.10/arch/arm/mm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
69 A 32-bit RISC microprocessor based on the ARM9 processor core
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
190 # ARM946E-S
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
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/Linux-v5.10/arch/arm64/kvm/vgic/
Dvgic-mmio.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include "vgic-mmio.h"
28 return -1UL; in vgic_mmio_read_rao()
53 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); in vgic_mmio_read_group()
55 if (irq->group) in vgic_mmio_read_group()
58 vgic_put_irq(vcpu->kvm, irq); in vgic_mmio_read_group()
66 WARN_ON(its_prop_update_vsgi(irq->host_irq, irq->priority, irq->group)); in vgic_update_vsgi()
77 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i); in vgic_mmio_write_group()
79 raw_spin_lock_irqsave(&irq->irq_lock, flags); in vgic_mmio_write_group()
80 irq->group = !!(val & BIT(i)); in vgic_mmio_write_group()
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