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/Linux-v6.6/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,mt8195-clock.yaml20 The devices except apusys_pll provide clock gate control in different IP blocks.
21 The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
51 - mediatek,mt8195-apusys_pll
234 apusys_pll: clock-controller@190f3000 {
235 compatible = "mediatek,mt8195-apusys_pll";
/Linux-v6.6/drivers/clk/mediatek/
Dclk-mt8195-apusys_pll.c99 { .compatible = "mediatek,mt8195-apusys_pll", },
108 .name = "clk-mt8195-apusys_pll",
DMakefile131 obj-$(CONFIG_COMMON_CLK_MT8195_APUSYS) += clk-mt8195-apusys_pll.o
/Linux-v6.6/include/dt-bindings/clock/
Dmt8195-clk.h733 /* APUSYS_PLL */
/Linux-v6.6/arch/arm64/boot/dts/mediatek/
Dmt8195.dtsi2506 apusys_pll: clock-controller@190f3000 { label
2507 compatible = "mediatek,mt8195-apusys_pll";