| /Linux-v6.6/arch/riscv/lib/ |
| D | uaccess.S | 43 * Copy first bytes until dst is aligned to word boundary.
45 * t1 - start of aligned dst
49 /* dst is already aligned, skip */
57 bltu a0, t1, 1b /* t1 - start of aligned dst */
61 * Now dst is aligned.
63 * Use word-copy if both src and dst are aligned because
72 * Both src and dst are aligned, unrolled word copy
74 * a0 - start of aligned dst
75 * a1 - start of aligned src
76 * t0 - end of aligned dst
[all …]
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| /Linux-v6.6/tools/testing/selftests/mm/ |
| D | mremap_test.c | 41 _1KB = 1ULL << 10, /* 1KB -> not page aligned */
253 * Check that the address is aligned to the specified alignment. in get_source_mapping()
256 * 2MB-aligned, however it will not be considered valid for a in get_source_mapping()
469 "mremap - Destination Address Misaligned (1KB-aligned)"); in main()
472 "mremap - Source Address Misaligned (1KB-aligned)"); in main()
474 /* Src addr PTE aligned */ in main()
477 "8KB mremap - Source PTE-aligned, Destination PTE-aligned"); in main()
479 /* Src addr 1MB aligned */ in main()
481 "2MB mremap - Source 1MB-aligned, Destination PTE-aligned"); in main()
483 "2MB mremap - Source 1MB-aligned, Destination 1MB-aligned"); in main()
[all …]
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| /Linux-v6.6/drivers/scsi/ |
| D | ipr.h | 333 }__attribute__((packed, aligned (4)));
411 }__attribute__ ((packed, aligned (4)));
434 }__attribute__ ((packed, aligned (8)));
441 }__attribute__((packed, aligned (4)));
448 }__attribute__((packed, aligned (4)));
453 }__attribute__((packed, aligned (4)));
458 }__attribute__((packed, aligned (8)));
473 }__attribute__((packed, aligned (4)));
481 }__attribute__((packed, aligned (4)));
543 }__attribute__ ((packed, aligned(4)));
[all …]
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| /Linux-v6.6/arch/xtensa/include/asm/ |
| D | coprocessor.h | 118 #define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
119 #define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
122 __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
124 __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
129 __attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
131 __attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
133 __attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
135 __attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
137 __attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
139 __attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
[all …]
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| /Linux-v6.6/arch/xtensa/lib/ |
| D | memset.S | 23 * If the destination is aligned,
27 * setting 1B and 2B and then go to aligned case.
29 * case of an aligned destination (except for the branches to
47 .L0: # return here from .Ldstunaligned when dst is aligned
54 * Destination is word-aligned.
56 # set 16 bytes per iteration for word-aligned dst
106 bbci.l a5, 0, .L20 # branch if dst alignment half-aligned
107 # dst is only byte aligned
112 # now retest if dst aligned
113 bbci.l a5, 1, .L0 # if now aligned, return to main algorithm
[all …]
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| D | memcopy.S | 34 * If source is aligned,
40 * case of aligned source and destination and multiple
89 .Ldst1mod2: # dst is only byte aligned
98 _bbci.l a5, 1, .Ldstaligned # if dst is now aligned, then
100 .Ldst2mod4: # dst 16-bit aligned
110 j .Ldstaligned # dst is now aligned, return to main algorithm
121 .Ldstaligned: # return here from .Ldst?mod? once dst is aligned
124 movi a8, 3 # if source is not aligned,
127 * Destination and source are word-aligned, use word copy.
129 # copy 16 bytes per iteration for word-aligned dst and word-aligned src
[all …]
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| D | usercopy.S | 30 * If the destination and source are both aligned,
33 * If destination is aligned and source unaligned,
38 * case of aligned destinations (except for the branches to
75 .Ldstaligned: # return here from .Ldstunaligned when dst is aligned
78 movi a8, 3 # if source is also aligned,
89 .Ldst1mod2: # dst is only byte aligned
98 bbci.l a5, 1, .Ldstaligned # if dst is now aligned, then
100 .Ldst2mod4: # dst 16-bit aligned
110 j .Ldstaligned # dst is now aligned, return to main algorithm
138 * Destination and source are word-aligned.
[all …]
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| D | checksum.S | 44 * is aligned on either a 2-byte or 4-byte boundary.
48 bnez a5, 8f /* branch if 2-byte aligned */
112 /* uncommon case, buf is 2-byte aligned */
118 bnez a5, 8f /* branch if 1-byte aligned */
124 j 1b /* now buf is 4-byte aligned */
126 /* case: odd-byte aligned, len > 1
188 This function is optimized for 4-byte aligned addresses. Other
199 aligned case. Two bbsi.l instructions might seem more optimal
206 beqz a9, 1f /* branch if both are 4-byte aligned */
208 j 3f /* one address is 2-byte aligned */
[all …]
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| /Linux-v6.6/drivers/scsi/pm8001/ |
| D | pm8001_hwi.h | 146 } __attribute__((packed, aligned(4)));
158 } __attribute__((packed, aligned(4)));
169 } __attribute__((packed, aligned(4)));
221 } __attribute__((packed, aligned(4)));
234 } __attribute__((packed, aligned(4)));
250 } __attribute__((packed, aligned(4)));
263 } __attribute__((packed, aligned(4)));
276 } __attribute__((packed, aligned(4)));
287 } __attribute__((packed, aligned(4)));
299 } __attribute__((packed, aligned(4)));
[all …]
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| D | pm80xx_hwi.h | 345 } __attribute__((packed, aligned(4)));
357 } __attribute__((packed, aligned(4)));
367 } __attribute__((packed, aligned(4)));
418 } __attribute__((packed, aligned(4)));
432 } __attribute__((packed, aligned(4)));
441 } __attribute__((packed, aligned(4)));
456 } __attribute__((packed, aligned(4)));
468 } __attribute__((packed, aligned(4)));
479 } __attribute__((packed, aligned(4)));
489 } __attribute__((packed, aligned(4)));
[all …]
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| /Linux-v6.6/include/uapi/linux/ |
| D | rseq.h | 41 * struct rseq_cs is aligned on 4 * 8 bytes to ensure it is always
54 } __attribute__((aligned(4 * sizeof(__u64))));
57 * struct rseq is aligned on 4 * 8 bytes to ensure it is always
67 * registered this data structure. Aligned on 32-bit. Always
80 * data structure. Aligned on 32-bit. Values
107 * thread which registered this data structure. Aligned on 64-bit.
138 * Aligned on 32-bit. Contains the current NUMA node ID.
146 * Aligned on 32-bit. Contains the current thread's concurrency ID
155 } __attribute__((aligned(4 * sizeof(__u64))));
|
| D | types.h | 17 typedef __signed__ __int128 __s128 __attribute__((aligned(16)));
18 typedef unsigned __int128 __u128 __attribute__((aligned(16)));
55 #define __aligned_u64 __u64 __attribute__((aligned(8)))
56 #define __aligned_be64 __be64 __attribute__((aligned(8)))
57 #define __aligned_le64 __le64 __attribute__((aligned(8)))
|
| D | swab.h | 169 * @p: pointer to a naturally-aligned 16-bit value
182 * @p: pointer to a naturally-aligned 32-bit value
195 * @p: pointer to a naturally-aligned 64-bit value
208 * @p: pointer to a naturally-aligned 32-bit value
223 * @p: pointer to a naturally-aligned 32-bit value
238 * @p: pointer to a naturally-aligned 16-bit value
250 * @p: pointer to a naturally-aligned 32-bit value
263 * @p: pointer to a naturally-aligned 64-bit value
276 * @p: pointer to a naturally-aligned 32-bit value
291 * @p: pointer to a naturally-aligned 32-bit value
|
| /Linux-v6.6/tools/testing/selftests/rseq/ |
| D | rseq-abi.h | 41 * struct rseq_abi_cs is aligned on 4 * 8 bytes to ensure it is always
54 } __attribute__((aligned(4 * sizeof(__u64))));
57 * struct rseq_abi is aligned on 4 * 8 bytes to ensure it is always
67 * registered this data structure. Aligned on 32-bit. Always
80 * data structure. Aligned on 32-bit. Values
107 * thread which registered this data structure. Aligned on 64-bit.
154 * Aligned on 32-bit. Contains the current NUMA node ID.
162 * Aligned on 32-bit. Contains the current thread's concurrency ID
171 } __attribute__((aligned(4 * sizeof(__u64))));
|
| /Linux-v6.6/drivers/staging/media/atomisp/pci/ |
| D | ia_css_env.h | 54 The address must be an 8 bit aligned address. */
57 The address must be a 16 bit aligned address. */
60 The address must be a 32 bit aligned address. */
63 space. The address must be an 8 bit aligned address. */
66 space. The address must be a 16 bit aligned address. */
69 space. The address must be a 32 bit aligned address. */
71 /** Store a number of bytes into a byte-aligned address in the CSS HW address space. */
73 /** Load a number of bytes from a byte-aligned address in the CSS HW address space. */
|
| /Linux-v6.6/arch/mips/kernel/ |
| D | cmpxchg.c | 16 /* Check that ptr is naturally aligned */ in __xchg_small()
25 * exchange within the naturally aligned 4 byte integer that includes in __xchg_small()
35 * Calculate a pointer to the naturally aligned 4 byte integer that in __xchg_small()
57 /* Check that ptr is naturally aligned */ in __cmpxchg_small()
67 * compare & exchange within the naturally aligned 4 byte integer in __cmpxchg_small()
77 * Calculate a pointer to the naturally aligned 4 byte integer that in __cmpxchg_small()
93 * Calculate the old & new values of the naturally aligned in __cmpxchg_small()
|
| /Linux-v6.6/arch/sparc/kernel/ |
| D | sstate.c | 38 static const char booting_msg[32] __attribute__((aligned(32))) =
40 static const char running_msg[32] __attribute__((aligned(32))) =
42 static const char halting_msg[32] __attribute__((aligned(32))) =
44 static const char poweroff_msg[32] __attribute__((aligned(32))) =
46 static const char rebooting_msg[32] __attribute__((aligned(32))) =
48 static const char panicking_msg[32] __attribute__((aligned(32))) =
|
| /Linux-v6.6/lib/ |
| D | iomap_copy.c | 11 * @to: destination, in MMIO space (must be 32-bit aligned)
12 * @from: source (must be 32-bit aligned)
34 * @to: destination (must be 32-bit aligned)
35 * @from: source, in MMIO space (must be 32-bit aligned)
55 * @to: destination, in MMIO space (must be 64-bit aligned)
56 * @from: source (must be 64-bit aligned)
|
| /Linux-v6.6/arch/arm64/lib/ |
| D | memset.S | 54 /*All store maybe are non-aligned..*/
70 /*Whether the start address is aligned with 16.*/
76 * then adjust the dst aligned with 16.This process will make the current
79 stp A_l, A_l, [dst] /*non-aligned store..*/
80 /*make the dst aligned..*/
103 * It will lead some bytes written twice and the access is non-aligned.
162 * Compute how far we need to go to become suitably aligned. We're
170 b.eq 2f /* Already aligned. */
171 /* Not aligned, check that there's enough to copy after alignment.*/
|
| /Linux-v6.6/arch/parisc/lib/ |
| D | io.c | 162 * SRC. SRC must be at least short aligned. This is used by the
179 case 0x00: /* Buffer 32-bit aligned */ in insw()
193 case 0x02: /* Buffer 16-bit aligned */ in insw()
210 case 0x01: /* Buffer 8-bit aligned */ in insw()
251 case 0x00: /* Buffer 32-bit aligned */ in insl()
259 case 0x02: /* Buffer 16-bit aligned */ in insl()
275 case 0x01: /* Buffer 8-bit aligned */ in insl()
292 case 0x03: /* Buffer 8-bit aligned */ in insl()
315 * Don't worry as much about doing aligned memory transfers:
349 case 0x00: /* Buffer 32-bit aligned */ in outsw()
[all …]
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| /Linux-v6.6/arch/nios2/lib/ |
| D | memcpy.c | 22 /* Type to use for aligned memory operations.
48 the assumption that DST_BP is aligned on an OPSIZ multiple. If
70 Both SRCP and DSTP should be aligned for memory operations on `op_t's. */
109 DSTP should be aligned for memory operations on `op_t's, but SRCP must
110 *not* be aligned. */
119 aligned srcp to make it aligned for copy. */ in _wordcopy_fwd_dest_aligned()
124 /* Make SRCP aligned by rounding it down to the beginning of the `op_t' in _wordcopy_fwd_dest_aligned()
169 /* Copy just a few bytes to make DSTP aligned. */ in memcpy()
|
| /Linux-v6.6/include/uapi/sound/ |
| D | compress_offload.h | 26 } __attribute__((packed, aligned(4)));
38 } __attribute__((packed, aligned(4)));
57 } __attribute__((packed, aligned(4)));
67 } __attribute__((packed, aligned(4)));
94 } __attribute__((packed, aligned(4)));
106 } __attribute__((packed, aligned(4)));
128 } __attribute__((packed, aligned(4)));
|
| /Linux-v6.6/drivers/gpu/drm/msm/disp/dpu1/ |
| D | msm_media_info.h | 46 * Y_Stride : Width aligned to 128
47 * UV_Stride : Width aligned to 128
48 * Y_Scanlines: Height aligned to 32
49 * UV_Scanlines: Height/2 aligned to 16
84 * Y_Stride : Width aligned to 128
85 * UV_Stride : Width aligned to 128
86 * Y_Scanlines: Height aligned to 32
87 * UV_Scanlines: Height/2 aligned to 16
142 * Y_Stride : Width aligned to 128
143 * UV_Stride : Width aligned to 128
[all …]
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| /Linux-v6.6/Documentation/driver-api/dmaengine/ |
| D | pxa_dma.rst | 100 - if Buffer1 and Buffer2 had all their addresses 8 bytes aligned
102 - and if Buffer3 has at least one address not 4 bytes aligned
107 this specific case if the DMA is already running in aligned mode.
146 - a driver submitted an aligned tx1, not chained
148 - a driver submitted an aligned tx2 => tx2 is cold chained to tx1
150 - a driver issued tx1+tx2 => channel is running in aligned mode
152 - a driver submitted an aligned tx3 => tx3 is hot-chained
159 - a driver submitted an aligned tx5 => tx5 is put in submitted queue, not
162 - a driver submitted an aligned tx6 => tx6 is put in submitted queue,
|
| /Linux-v6.6/arch/sparc/lib/ |
| D | M7memset.S | 144 andcc %o5, 7, %o3 ! is sp1 aligned on a 8 byte bound?
145 bz,pt %xcc, .blkalign ! already long word aligned
146 sub %o3, 8, %o3 ! -(bytes till long word aligned)
149 ! Set -(%o3) bytes till sp1 long word aligned
155 ! Now sp1 is long word aligned (sp1 is found in %o5)
161 andcc %o5, 63, %o3 ! is sp1 block aligned?
162 bz,pt %xcc, .blkwr ! now block aligned
163 sub %o3, 64, %o3 ! o3 is -(bytes till block aligned)
166 ! Store -(%o3) bytes till dst is block (64 byte) aligned.
168 ! Recall that dst is already long word aligned
[all …]
|
