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/Linux-v5.10/drivers/zorro/
Dzorro.ids21 0000 Stormbringer [Accelerator]
22 1300 Warp Engine [Accelerator, SCSI Host Adapter and RAM Expansion]
40 5000 A2620 68020 [Accelerator and RAM Expansion]
41 5100 A2630 68030 [Accelerator and RAM Expansion]
52 6900 A2000 68040 [Accelerator]
53 9600 68040 [Accelerator]
76 4500 VXL-30 [Accelerator]
90 3900 Hurricane 2800 [Accelerator and RAM Expansion]
91 5700 Hurricane 2800 [Accelerator and RAM Expansion]
112 1100 Magnum 40 [Accelerator and SCSI Host Adapter]
[all …]
/Linux-v5.10/drivers/crypto/
DKconfig75 + Crypto Express 2 up to 7 Accelerator (CEXxA)
270 tristate "Driver HIFN 795x crypto accelerator chips"
336 tristate "Driver AMCC PPC4xx crypto accelerator"
367 tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator"
375 OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you
389 OMAP processors have AES module accelerator. Select this if you
399 OMAP processors have DES/3DES module accelerator. Select this if you
425 tristate "Support for SAHARA crypto accelerator"
431 This option enables support for the SAHARA HW crypto accelerator
450 tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
[all …]
/Linux-v5.10/drivers/crypto/hisilicon/
DKconfig4 tristate "Support for Hisilicon SEC crypto block cipher accelerator"
18 tristate "Support for HiSilicon SEC2 crypto block cipher accelerator"
48 HiSilicon accelerator engines use a common queue management
52 tristate "Support for HiSilicon ZIP accelerator"
63 tristate "Support for HISI HPRE accelerator"
73 accelerator, which can accelerate RSA and DH algorithms.
/Linux-v5.10/Documentation/devicetree/bindings/crypto/
Dimg-hash.txt1 Imagination Technologies hardware hash accelerator
3 The hash accelerator provides hardware hashing acceleration for
8 - compatible : "img,hash-accelerator"
15 "hash" Used to clock data through the accelerator
20 compatible = "img,hash-accelerator";
Dxlnx,zynqmp-aes.yaml7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
Drockchip-crypto.txt1 Rockchip Electronics And Security Accelerator
11 "sclk" used to clock crypto accelerator
/Linux-v5.10/Documentation/devicetree/bindings/dma/
Dste-dma40.txt110 48: Crypto Accelerator 1
111 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
112 50: Hash Accelerator 1 TX
123 61: Crypto Accelerator 0
124 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
125 63: Hash Accelerator 0 TX
/Linux-v5.10/drivers/staging/media/atomisp/pci/isp/kernels/sdis/common/
Dia_css_sdis_common_types.h114 /* DVS statistics generated by accelerator global configuration
125 /* DVS statistics generated by accelerator level grid
139 /* DVS statistics generated by accelerator level grid start
151 /* DVS statistics generated by accelerator level grid end
161 /* DVS statistics generated by accelerator Feature Extraction
175 /* DVS statistics generated by accelerator public configuration
186 /* DVS statistics grid generated by accelerator
198 /* DVS statistics generated by accelerator default grid info
215 /** DVS statistics produced by accelerator grid info */
/Linux-v5.10/Documentation/misc-devices/
Duacce.rst6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
8 So accelerator can access any data structure of the main cpu.
13 Uacce takes the hardware accelerator as a heterogeneous processor, while
21 | User application (CPU) | | Hardware Accelerator |
95 The accelerator device present itself as an Uacce object, which exports as
175 match the right accelerator accordingly.
/Linux-v5.10/drivers/crypto/stm32/
DKconfig8 This enables support for the CRC32 hw accelerator which can be found
21 This enables support for the HASH hw accelerator which can be found
31 This enables support for the CRYP (AES/DES/TDES) hw accelerator which
/Linux-v5.10/Documentation/powerpc/
Dcxl.rst2 Coherent Accelerator Interface (CXL)
8 The coherent accelerator interface is designed to allow the
11 Accelerator Interface Architecture (CAIA).
13 IBM refers to this as the Coherent Accelerator Processor Interface
17 Coherent in this context means that the accelerator and CPUs can
46 The POWER Service Layer (PSL) and the Accelerator Function Unit
52 The AFU is the core part of the accelerator (eg. the compression,
86 this mode, only one userspace process can use the accelerator at
91 applications may use the accelerator (although specific AFUs may
102 A portion of the accelerator MMIO space can be directly mapped
[all …]
Dvas-api.rst5 Virtual Accelerator Switchboard (VAS) userspace API
11 Power9 processor introduced Virtual Accelerator Switchboard (VAS) which
13 (hardware accelerator) referred to as the Nest Accelerator (NX). The NX
31 requests directly to NX accelerator.
82 accelerator. It finds CPU on which the user process is executing and
/Linux-v5.10/drivers/misc/ocxl/
DKconfig3 # Open Coherent Accelerator (OCXL) compatible devices
11 tristate "OpenCAPI coherent accelerator support"
17 Coherent Accelerator Processor Interface (OpenCAPI) devices.
/Linux-v5.10/Documentation/devicetree/bindings/powerpc/4xx/
Dppc440spe-adma.txt1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
60 iii) XOR Accelerator node
64 - compatible : "amcc,xor-accelerator";
71 compatible = "amcc,xor-accelerator";
/Linux-v5.10/drivers/net/ethernet/chelsio/inline_crypto/
DKconfig22 Support Chelsio Inline TLS with Chelsio crypto accelerator.
34 Support Chelsio Inline IPsec with Chelsio crypto accelerator.
47 crypto accelerator. CONFIG_CHELSIO_TLS_DEVICE flag can be enabled
/Linux-v5.10/Documentation/devicetree/bindings/soc/ti/
Dk3-ringacc.yaml8 title: Texas Instruments K3 NavigatorSS Ring Accelerator
15 The Ring Accelerator (RA) is a machine which converts read/write accesses
25 The Ring Accelerator is a hardware module that is responsible for accelerating
63 description: TI-SCI device id of the ring accelerator
/Linux-v5.10/arch/sh/include/asm/
Dhd64461.h93 #define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
95 #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
96 #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
97 #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
98 #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
99 #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */
100 #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
/Linux-v5.10/drivers/misc/genwqe/
DKconfig3 # IBM Accelerator Family 'GenWQE'
7 tristate "GenWQE PCIe Accelerator"
/Linux-v5.10/Documentation/devicetree/bindings/arm/omap/
Diva.txt1 * TI - IVA (Imaging and Video Accelerator) subsystem
3 The IVA contain various audio, video or imaging HW accelerator
/Linux-v5.10/drivers/soc/ti/
DKconfig84 bool "K3 Ring accelerator Sub System"
88 Say y here to support the K3 Ring accelerator module.
89 The Ring Accelerator (RINGACC or RA) provides hardware acceleration
/Linux-v5.10/drivers/misc/cxl/
DKconfig3 # IBM Coherent Accelerator (CXL) compatible devices
17 Accelerators (CXL). CXL is otherwise known as Coherent Accelerator
/Linux-v5.10/drivers/crypto/marvell/
DKconfig19 Security Accelerator (CESA) which can be found on MVEBU and ORION
34 Accelerator Unit(CPT) found in OcteonTX series of processors.
/Linux-v5.10/drivers/crypto/qat/qat_common/
Dadf_cfg_strings.h8 #define ADF_ACCEL_SEC "Accelerator"
36 #define ADF_ACCEL_STR "Accelerator%d"
/Linux-v5.10/drivers/staging/media/atomisp/pci/
Dia_css_acc_types.h48 IA_CSS_ACC_OUTPUT, /** Accelerator stage on output frame */
49 IA_CSS_ACC_VIEWFINDER, /** Accelerator stage on viewfinder frame */
360 /* Accelerator firmware information.
372 struct ia_css_acc_info acc; /** Accelerator info */
404 /* Structure describing the SP binary of a stand-alone accelerator.
423 enum ia_css_acc_type type; /** Type of accelerator */
439 * For a pipeline stage accelerator, it contains ISP code only.
/Linux-v5.10/arch/powerpc/platforms/powernv/
DKconfig37 bool "IBM Virtual Accelerator Switchboard (VAS)"
41 This enables support for IBM Virtual Accelerator Switchboard (VAS).

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