| /Linux-v5.10/Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
89 That covers the general approach to binding xilinx IP cores into the
92 i) Xilinx ML300 Framebuffer
105 ii) Xilinx SystemACE
107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
114 iii) Xilinx EMAC and Xilinx TEMAC
116 Xilinx Ethernet devices. In addition to general xilinx properties
121 iv) Xilinx Uartlite
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| /Linux-v5.10/drivers/net/ethernet/xilinx/ |
| D | Kconfig | 7 bool "Xilinx devices"
14 the questions about Xilinx devices. If you say Y, you will be asked
20 tristate "Xilinx 10/100 Ethernet Lite support"
24 This driver supports the 10/100 Ethernet Lite from Xilinx.
27 tristate "Xilinx 10/100/1000 AXI Ethernet support"
30 This driver supports the 10/100/1000 Ethernet from Xilinx for the
31 AXI bus interface used in Xilinx Virtex FPGAs and Soc's.
34 tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
37 This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
38 core used in Xilinx Spartan and Virtex FPGAs
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | xilinx.yaml | 4 $id: http://devicetree.org/schemas/arm/xilinx.yaml#
7 title: Xilinx Zynq Platforms Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
49 - description: Xilinx internal board zc1232
55 - description: Xilinx internal board zc1254
61 - description: Xilinx internal board zc1275
67 - description: Xilinx 96boards compatible board zcu100
73 - description: Xilinx 96boards compatible board Ultra96
81 - description: Xilinx evaluation board zcu102
[all …]
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| /Linux-v5.10/drivers/media/platform/xilinx/ |
| D | Makefile | 3 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
5 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
6 obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
7 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
8 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
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| D | Kconfig | 4 tristate "Xilinx Video IP (EXPERIMENTAL)"
11 Driver for Xilinx Video IP Pipelines
16 tristate "Xilinx CSI-2 Rx Subsystem"
18 Driver for Xilinx MIPI CSI-2 Rx Subsystem. This is a V4L sub-device
23 tristate "Xilinx Video Test Pattern Generator"
27 Driver for the Xilinx Video Test Pattern Generator
30 tristate "Xilinx Video Timing Controller"
33 Driver for the Xilinx Video Timing Controller
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| D | xilinx-vipp.h | 3 * Xilinx Video IP Composite Device
6 * Copyright (C) 2013-2015 Xilinx, Inc.
8 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
23 * struct xvip_composite_device - Xilinx Video IP device structure
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| /Linux-v5.10/sound/soc/xilinx/ |
| D | Kconfig | 3 tristate "Audio support for the Xilinx I2S"
5 Select this option to enable Xilinx I2S Audio. This enables
6 I2S playback and capture using xilinx soft IP. In transmitter
12 tristate "Audio support for the Xilinx audio formatter"
14 Select this option to enable Xilinx audio formatter
19 tristate "Audio support for the Xilinx SPDIF"
21 Select this option to enable Xilinx SPDIF Audio.
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| /Linux-v5.10/Documentation/ABI/stable/ |
| D | sysfs-driver-firmware-zynqmp | 4 Contact: "Jolly Shah" <jollys@xilinx.com>
13 other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}.
25 Users: Xilinx
30 Contact: "Jolly Shah" <jollys@xilinx.com>
40 Four registers are used by the FSBL and other Xilinx
54 Users: Xilinx
59 Contact: "Jolly Shah" <jollys@xilinx.com>
91 Users: Xilinx
96 Contact: "Jolly Shah" <jollys@xilinx.com>
115 Users: Xilinx
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| /Linux-v5.10/drivers/irqchip/ |
| D | irq-xilinx-intc.c | 3 * Copyright (C) 2012-2013 Xilinx, Inc.
67 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); in intc_enable_or_unmask()
83 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); in intc_disable_or_mask()
91 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); in intc_ack()
100 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); in intc_mask_ack()
106 .name = "Xilinx INTC",
122 pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); in xintc_get_irq_local()
136 pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq); in xintc_get_irq()
194 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); in xilinx_intc_of_init()
200 pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); in xilinx_intc_of_init()
[all …]
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| /Linux-v5.10/drivers/firmware/xilinx/ |
| D | zynqmp-debug.h | 3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2018 Xilinx
7 * Michal Simek <michal.simek@xilinx.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
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| /Linux-v5.10/drivers/staging/gs_fpgaboot/ |
| D | README | 2 Linux Driver Source for Xilinx FPGA firmware download
16 - Download Xilinx FPGA firmware
17 - This module downloads Xilinx FPGA firmware using gpio pins.
28 - load Xilinx FPGA bitstream format[1] firmware image file using
30 - program the Xilinx FPGA using SelectMAP (parallel) mode [2]
67 1. Xilinx APP NOTE XAPP583:
68 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
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| /Linux-v5.10/arch/microblaze/pci/ |
| D | xilinx_pci.c | 2 * PCI support for Xilinx plbv46_pci soft-core which can be used on
3 * Xilinx Virtex ML410 / ML510 boards.
36 * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
62 dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n", in xilinx_pci_fixup_bridge()
120 * xilinx_pci_init - Find and register a Xilinx PCI host bridge
134 pr_err("xilinx-pci: cannot resolve base address\n"); in xilinx_pci_init()
140 pr_err("xilinx-pci: pcibios_alloc_controller() failed\n"); in xilinx_pci_init()
149 /* According to the xilinx plbv46_pci documentation the soft-core starts in xilinx_pci_init()
168 pr_info("xilinx-pci: Registered PCI host bridge\n"); in xilinx_pci_init()
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| /Linux-v5.10/drivers/net/ethernet/sfc/ |
| D | ef100.c | 5 * Copyright 2019-2020 Xilinx Inc.
32 /* Expected size of a Xilinx continuation address table entry. */
86 "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n", in ef100_pci_parse_ef100_entry()
104 /* Parse a Xilinx capabilities table entry describing a continuation to a new
128 "Bad BAR value of %d in Xilinx capabilities sub-table.\n", in ef100_pci_parse_continue_entry()
138 "Xilinx table will overrun BAR[%d] offset=0x%llx\n", in ef100_pci_parse_continue_entry()
149 "Mapping new BAR for Xilinx table failed, rc=%d\n", rc); in ef100_pci_parse_continue_entry()
175 /* Iterate over the Xilinx capabilities table in the currently mapped BAR and
197 "Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n", in ef100_pci_walk_xilinx_table()
202 "Xilinx table entry too short len=0x%x\n", entry_size); in ef100_pci_walk_xilinx_table()
[all …]
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| /Linux-v5.10/drivers/char/xilinx_hwicap/ |
| D | buffer_icap.h | 3 * Author: Xilinx, Inc.
10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
24 * (c) Copyright 2003-2008 Xilinx Inc.
|
| D | fifo_icap.h | 3 * Author: Xilinx, Inc.
10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
24 * (c) Copyright 2007-2008 Xilinx Inc.
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | xlnx,versal-clk.yaml | 7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@xilinx.com>
11 - Jolly Shah <jolly.shah@xilinx.com>
12 - Rajan Vaja <rajan.vaja@xilinx.com>
15 The clock controller is a hardware block of Xilinx versal clock tree. It
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| /Linux-v5.10/drivers/fpga/ |
| D | Kconfig | 56 tristate "Xilinx Zynq FPGA"
59 FPGA manager driver support for Xilinx Zynq FPGAs.
68 tristate "Xilinx Configuration over Slave Serial (SPI)"
71 FPGA manager driver support for Xilinx FPGA configuration
117 tristate "Xilinx LogiCORE PR Decoupler"
121 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
211 tristate "Xilinx ZynqMP FPGA"
214 FPGA manager driver support for Xilinx ZynqMP FPGAs.
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| /Linux-v5.10/drivers/staging/axis-fifo/ |
| D | Kconfig | 3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
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| /Linux-v5.10/sound/pci/mixart/ |
| D | mixart_hwdep.c | 338 /* read motherboard xilinx status */ in mixart_dsp_load()
342 /* read daughterboard xilinx status */ in mixart_dsp_load()
345 /* motherboard xilinx status 5 will say that the board is performing a reset */ in mixart_dsp_load()
354 /* xilinx already loaded ? */ in mixart_dsp_load()
356 dev_dbg(&mgr->pci->dev, "xilinx is already loaded !\n"); in mixart_dsp_load()
362 "xilinx load error ! status = %d\n", in mixart_dsp_load()
367 /* check xilinx validity */ in mixart_dsp_load()
373 /* set xilinx status to copying */ in mixart_dsp_load()
376 /* setup xilinx base address */ in mixart_dsp_load()
378 /* setup code size for xilinx file */ in mixart_dsp_load()
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/fpga/ |
| D | xilinx-slave-serial.txt | 1 Xilinx Slave Serial SPI FPGA Manager
3 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
9 - https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
10 - https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
11 - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
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| /Linux-v5.10/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zc1254-revA.dts | 3 * dts file for Xilinx ZynqMP ZC1254
5 * (C) Copyright 2015 - 2019, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
8 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
|
| D | zynqmp-zc1275-revA.dts | 3 * dts file for Xilinx ZynqMP ZC1275
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
7 * Michal Simek <michal.simek@xilinx.com>
8 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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| /Linux-v5.10/drivers/usb/host/ |
| D | ehci-xilinx-of.c | 5 * Bus Glue for Xilinx EHCI core on the of_platform bus
7 * Copyright (c) 2009 Xilinx, Inc.
27 * This function is used as a place to tell the user that the Xilinx USB host
112 * host controller. Because the Xilinx USB host controller can be configured
129 dev_dbg(&op->dev, "initializing XILINX-OF USB Controller\n"); in ehci_hcd_xilinx_of_probe()
136 "XILINX-OF USB"); in ehci_hcd_xilinx_of_probe()
204 dev_dbg(&op->dev, "stopping XILINX-OF USB Controller\n"); in ehci_hcd_xilinx_of_remove()
224 .name = "xilinx-of-ehci",
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| /Linux-v5.10/include/uapi/linux/ |
| D | xilinx-v4l2-controls.h | 3 * Xilinx Controls Header
6 * Copyright (C) 2013-2015 Xilinx, Inc.
8 * Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
30 * Private Controls for Xilinx Video IPs
34 * Xilinx TPG Video IP
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| /Linux-v5.10/Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.txt | 1 Xilinx IPI Mailbox Controller
4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
9 | Xilinx ZynqMP IPI Controller |
26 | Xilinx IPI Agent Block |
39 - xlnx,ipi-id: local Xilinx IPI agent ID
60 - xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
|
