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/Linux-v6.1/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_wp.c21 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
45 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
47 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
50 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
52 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
54 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
57 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
59 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
62 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
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Dhdmi.h41 /* HDMI WP IRQ flags */
233 struct hdmi_wp_data *wp; member
277 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
278 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
279 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
280 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
281 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
282 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
283 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
284 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
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Dhdmi5.c64 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
67 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
68 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
80 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
92 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
95 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
100 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
102 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
177 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); in hdmi_power_on_full()
178 hdmi_wp_set_irqstatus(&hdmi.wp, in hdmi_power_on_full()
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Dhdmi4.c60 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
63 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
64 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
74 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
76 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
79 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
83 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
147 struct hdmi_wp_data *wp = &hdmi.wp; in hdmi_power_on_full() local
155 hdmi_wp_clear_irqenable(wp, 0xffffffff); in hdmi_power_on_full()
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Dhdmi_pll.c102 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
106 return hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
112 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
114 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
209 struct hdmi_wp_data *wp) in hdmi_pll_init() argument
213 pll->wp = wp; in hdmi_pll_init()
/Linux-v6.1/drivers/gpu/drm/omapdrm/dss/
Dhdmi_wp.c20 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
44 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
46 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
49 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
51 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
53 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
56 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
58 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
61 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
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Dhdmi.h45 /* HDMI WP IRQ flags */
239 struct hdmi_wp_data *wp; member
261 struct hdmi_wp_data *wp; member
296 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
297 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
298 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
299 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
300 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
301 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
302 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
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Dhdmi5.c68 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler() local
71 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
72 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
84 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
96 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
99 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
104 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
106 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
172 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff); in hdmi_power_on_full()
173 hdmi_wp_set_irqstatus(&hdmi->wp, in hdmi_power_on_full()
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Dhdmi4.c67 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler() local
70 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
71 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
83 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
86 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
88 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
90 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
150 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_power_on_full() local
159 hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE); in hdmi_power_on_full()
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Dhdmi_pll.c42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
50 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
60 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
63 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
147 if (hpll->wp->version == 4) in hdmi_init_pll_data()
162 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) in hdmi_pll_init() argument
167 pll->wp = wp; in hdmi_pll_init()
Dhdmi4_cec.c164 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
165 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
166 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
178 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi_cec_adap_enable()
201 hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
238 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
326 struct hdmi_wp_data *wp) in hdmi4_cec_init() argument
337 core->wp = wp; in hdmi4_cec_init()
340 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi4_cec_init()
/Linux-v6.1/arch/powerpc/math-emu/
Dmath_efp.c109 u32 wp[2]; member
200 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
201 vc.wp[1] = regs->gpr[fc]; in do_spe_mathemu()
202 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
203 va.wp[1] = regs->gpr[fa]; in do_spe_mathemu()
204 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
205 vb.wp[1] = regs->gpr[fb]; in do_spe_mathemu()
210 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
211 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
212 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
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/Linux-v6.1/lib/mpi/
Dmpi-add.c22 mpi_ptr_t wp, up; in mpi_add_ui() local
37 wp = w->d; in mpi_add_ui()
40 wp[0] = v; in mpi_add_ui()
44 cy = mpihelp_add_1(wp, up, usize, v); in mpi_add_ui()
45 wp[usize] = cy; in mpi_add_ui()
52 wp[0] = v - up[0]; in mpi_add_ui()
55 mpihelp_sub_1(wp, up, usize, v); in mpi_add_ui()
57 wsize = usize - (wp[usize-1] == 0); in mpi_add_ui()
69 mpi_ptr_t wp, up, vp; in mpi_add() local
94 wp = w->d; in mpi_add()
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Dmpi-mul.c19 mpi_ptr_t up, vp, wp; in mpi_mul() local
42 wp = w->d; in mpi_mul()
47 if (wp == up || wp == vp) { in mpi_mul()
48 wp = mpi_alloc_limb_space(wsize); in mpi_mul()
52 wp = w->d; in mpi_mul()
55 if (wp == up) { in mpi_mul()
59 if (wp == vp) in mpi_mul()
62 MPN_COPY(up, wp, usize); in mpi_mul()
63 } else if (wp == vp) { in mpi_mul()
67 MPN_COPY(vp, wp, vsize); in mpi_mul()
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Dgeneric_mpih-lshift.c19 * and store the USIZE least significant digits of the result at WP.
24 * 2. If the result is to be written over the input, WP must be >= UP.
28 mpihelp_lshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned int cnt) in mpihelp_lshift() argument
36 wp += 1; in mpihelp_lshift()
44 wp[i] = (high_limb << sh_1) | (low_limb >> sh_2); in mpihelp_lshift()
47 wp[i] = high_limb << sh_1; in mpihelp_lshift()
Dgeneric_mpih-rshift.c20 * and store the USIZE least significant limbs of the result at WP.
25 * 2. If the result is to be written over the input, WP must be <= UP.
29 mpihelp_rshift(mpi_ptr_t wp, mpi_ptr_t up, mpi_size_t usize, unsigned cnt) in mpihelp_rshift() argument
37 wp -= 1; in mpihelp_rshift()
44 wp[i] = (low_limb >> sh_1) | (high_limb << sh_2); in mpihelp_rshift()
47 wp[i] = low_limb >> sh_1; in mpihelp_rshift()
Dec.c182 static void mpih_set_cond(mpi_ptr_t wp, mpi_ptr_t up, in mpih_set_cond() argument
190 x = mask & (wp[i] ^ up[i]); in mpih_set_cond()
191 wp[i] = wp[i] ^ x; in mpih_set_cond()
201 mpi_ptr_t wp, up, vp; in ec_addm_25519() local
212 wp = w->d; in ec_addm_25519()
214 mpihelp_add_n(wp, up, vp, wsize); in ec_addm_25519()
215 borrow = mpihelp_sub_n(wp, wp, ctx->p->d, wsize); in ec_addm_25519()
217 mpihelp_add_n(wp, wp, n, wsize); in ec_addm_25519()
218 wp[LIMB_SIZE_25519-1] &= ~((mpi_limb_t)1 << (255 % BITS_PER_MPI_LIMB)); in ec_addm_25519()
223 mpi_ptr_t wp, up, vp; in ec_subm_25519() local
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/Linux-v6.1/tools/testing/selftests/breakpoints/
Dbreakpoint_test_arm64.c81 static bool set_watchpoint(pid_t pid, int size, int wp) in set_watchpoint() argument
83 const volatile uint8_t *addr = &var[32 + wp]; in set_watchpoint()
112 static bool run_test(int wr_size, int wp_size, int wr, int wp) in run_test() argument
143 if (!set_watchpoint(pid, wp_size, wp)) in run_test()
204 int wr, wp, size; in main() local
216 for (wp = wr - size; wp <= wr + size; wp = wp + size) { in main()
217 result = run_test(size, MIN(size, 8), wr, wp); in main()
218 if ((result && wr == wp) || in main()
219 (!result && wr != wp)) in main()
222 size, wr, wp); in main()
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/Linux-v6.1/lib/raid6/
Dneon.uc62 register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
70 wq$$ = wp$$ = vld1q_u8(&dptr[z0][d+$$*NSIZE]);
73 wp$$ = veorq_u8(wp$$, wd$$);
81 vst1q_u8(&p[d+NSIZE*$$], wp$$);
93 register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
102 wp$$ = veorq_u8(vld1q_u8(&p[d+$$*NSIZE]), wq$$);
107 wp$$ = veorq_u8(wp$$, wd$$);
149 vst1q_u8(&p[d+NSIZE*$$], wp$$);
Dint.uc88 unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
95 wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
98 wp$$ ^= wd$$;
105 *(unative_t *)&p[d+NSIZE*$$] = wp$$;
117 unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
125 wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
128 wp$$ ^= wd$$;
142 *(unative_t *)&p[d+NSIZE*$$] ^= wp$$;
/Linux-v6.1/tools/perf/tests/
Dbp_account.c88 TEST_ASSERT_VAL("failed to create wp\n", fd[i] != -1); in bp_accounting()
89 pr_debug("wp %d created\n", i); in bp_accounting()
97 TEST_ASSERT_VAL("failed to modify wp\n", ret == 0); in bp_accounting()
99 pr_debug("wp 0 modified to bp\n"); in bp_accounting()
103 TEST_ASSERT_VAL("failed to create max wp\n", fd_wp != -1); in bp_accounting()
104 pr_debug("wp max created\n"); in bp_accounting()
166 pr_err("failed to create wp\n"); in detect_share()
197 * - in case wp and bp do not share slots,
/Linux-v6.1/sound/hda/
Dhdac_controller.c70 bus->rirb.wp = bus->rirb.rp = 0; in snd_hdac_bus_init_cmd_io()
145 unsigned int wp, rp; in snd_hdac_bus_send_cmd() local
152 wp = snd_hdac_chip_readw(bus, CORBWP); in snd_hdac_bus_send_cmd()
153 if (wp == 0xffff) { in snd_hdac_bus_send_cmd()
158 wp++; in snd_hdac_bus_send_cmd()
159 wp %= AZX_MAX_CORB_ENTRIES; in snd_hdac_bus_send_cmd()
162 if (wp == rp) { in snd_hdac_bus_send_cmd()
169 bus->corb.buf[wp] = cpu_to_le32(val); in snd_hdac_bus_send_cmd()
170 snd_hdac_chip_writew(bus, CORBWP, wp); in snd_hdac_bus_send_cmd()
189 unsigned int rp, wp; in snd_hdac_bus_update_rirb() local
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/Linux-v6.1/Documentation/mhi/
Dmhi.rst96 [Write Pointer (WP)]- [Ring Element]
106 * Ring is considered empty when RP == WP.
107 * Ring is considered full when WP + 1 == RP.
110 buffer information, increments the WP to the next element and rings the
123 [Write Pointer (WP)]- [Ring Element]
133 * Both host and device has a local copy of RP, WP.
134 * Ring is considered empty (no events to service) when WP + 1 == RP.
135 * Ring is considered full of events when RP == WP.
209 * Host increments the WP of the corresponding channel transfer ring.
216 * Host updates the WP of the corresponding event ring to indicate that the
/Linux-v6.1/Documentation/virt/kvm/x86/
Dmmu.rst66 pages, pae, pse, pse36, cr0.wp, and 1GB pages. Emulated hardware also
186 Contains the value of cr0.wp for which the page is valid.
188 Contains the value of cr4.smep && !cr0.wp for which the page is valid
190 treatment of cr0.wp=0 below).
192 Contains the value of cr4.smap && !cr0.wp for which the page is valid
194 treatment of cr0.wp=0 below).
376 Emulating cr0.wp
379 If tdp is not enabled, the host must keep cr0.wp=1 so page write protection
381 cr0.wp=1, this does not present a problem. However when the guest cr0.wp=0,
404 CR4.SMAP && !CR0.WP into shadow page's role to avoid this case. Note,
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/Linux-v6.1/drivers/block/null_blk/
Dzoned.c130 zone->wp = zone->start + zone->len; in null_init_zoned_dev()
141 zone->start = zone->wp = sector; in null_init_zoned_dev()
218 blkz.wp = zone->wp; in null_report_zones()
245 sector + nr_sectors <= zone->wp) in null_zone_valid_read_len()
248 if (sector > zone->wp) in null_zone_valid_read_len()
251 return (zone->wp - sector) << SECTOR_SHIFT; in null_zone_valid_read_len()
273 if (zone->wp == zone->start) { in __null_close_zone()
400 sector = zone->wp; in null_zone_write()
405 } else if (sector != zone->wp) { in null_zone_write()
410 if (zone->wp + nr_sectors > zone->start + zone->capacity) { in null_zone_write()
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