| /Linux-v6.1/drivers/gpu/drm/radeon/ |
| D | rs780_dpm.c | 570 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_before_set_eng_clock()
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_before_set_eng_clock()
587 if ((new_ps->vclk == old_ps->vclk) && in rs780_set_uvd_clock_after_set_eng_clock()
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rs780_set_uvd_clock_after_set_eng_clock()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
735 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rs780_parse_pplib_non_clock_info()
736 rps->vclk = RS780_DEFAULT_VCLK_FREQ; in rs780_parse_pplib_non_clock_info()
945 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_print_power_state()
994 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rs780_dpm_debugfs_print_current_performance_level()
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| D | radeon_uvd.c | 933 * @vclk: wanted VCLK
943 * @optimal_vclk_div: resulting vclk post divider
950 unsigned vclk, unsigned dclk, in radeon_uvd_calc_upll_dividers() argument
965 vco_min = max(max(vco_min, vclk), dclk); in radeon_uvd_calc_upll_dividers()
979 /* calc vclk divider with current vco freq */ in radeon_uvd_calc_upll_dividers()
980 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
992 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
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| D | sumo_dpm.c | 824 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in sumo_setup_uvd_clocks()
840 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_before_set_eng_clock()
858 if ((new_rps->vclk == old_rps->vclk) && in sumo_set_uvd_clock_after_set_eng_clock()
1414 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in sumo_parse_pplib_non_clock_info()
1417 rps->vclk = 0; in sumo_parse_pplib_non_clock_info()
1802 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_print_power_state()
1825 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
1833 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in sumo_dpm_debugfs_print_current_performance_level()
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| D | trinity_dpm.c | 854 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
866 if ((rps1->vclk == rps2->vclk) && in trinity_uvd_clocks_equal()
899 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
910 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk); in trinity_setup_uvd_clocks()
1414 if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) && in trinity_get_uvd_clock_index()
1648 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in trinity_parse_pplib_non_clock_info()
1651 rps->vclk = 0; in trinity_parse_pplib_non_clock_info()
1889 pi->sys_info.uvd_clock_table_entries[i].vclk = in trinity_parse_sys_info_table()
1975 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_print_power_state()
2000 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in trinity_dpm_debugfs_print_current_performance_level()
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| D | rv6xx_dpm.c | 1518 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_before_set_eng_clock()
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_before_set_eng_clock()
1535 if ((new_ps->vclk == old_ps->vclk) && in rv6xx_set_uvd_clock_after_set_eng_clock()
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv6xx_set_uvd_clock_after_set_eng_clock()
1803 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1806 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
2015 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_print_power_state()
2047 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv6xx_dpm_debugfs_print_current_performance_level()
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| D | rv770_dpm.c | 1440 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_before_set_eng_clock()
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_before_set_eng_clock()
1457 if ((new_ps->vclk == old_ps->vclk) && in rv770_set_uvd_clock_after_set_eng_clock()
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in rv770_set_uvd_clock_after_set_eng_clock()
2155 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2158 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) { in rv7xx_parse_pplib_non_clock_info()
2164 rps->vclk = RV770_DEFAULT_VCLK_FREQ; in rv7xx_parse_pplib_non_clock_info()
2442 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_print_power_state()
2486 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in rv770_dpm_debugfs_print_current_performance_level()
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| /Linux-v6.1/Documentation/devicetree/bindings/media/ |
| D | aspeed-video.txt | 13 - clock-names: "vclk" and "eclk"
29 clock-names = "vclk", "eclk";
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| /Linux-v6.1/drivers/video/fbdev/nvidia/ |
| D | nv_hw.c | 380 static void nv4UpdateArbitrationSettings(unsigned VClk, in nv4UpdateArbitrationSettings() argument
402 sim_data.pclk_khz = VClk; in nv4UpdateArbitrationSettings()
618 static void nv10UpdateArbitrationSettings(unsigned VClk, in nv10UpdateArbitrationSettings() argument
642 sim_data.pclk_khz = VClk; in nv10UpdateArbitrationSettings()
676 static void nForceUpdateArbitrationSettings(unsigned VClk, in nForceUpdateArbitrationSettings() argument
744 sim_data.pclk_khz = VClk; in nForceUpdateArbitrationSettings()
771 unsigned VClk, Freq; in CalcVClock() local
776 VClk = (unsigned)clockIn; in CalcVClock()
787 Freq = VClk << P; in CalcVClock()
790 N = ((VClk << P) * M) / par->CrystalFreqKHz; in CalcVClock()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,fimd.yaml | 46 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
119 samsung,invert-vclk:
185 samsung,invert-vclk;
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| /Linux-v6.1/drivers/gpu/drm/exynos/ |
| D | exynos7_drm_decon.c | 51 struct clk *vclk; member
148 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); in decon_calc_clkdiv()
724 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); in decon_probe()
725 if (IS_ERR(ctx->vclk)) { in decon_probe()
727 ret = PTR_ERR(ctx->vclk); in decon_probe()
787 clk_disable_unprepare(ctx->vclk); in exynos7_decon_suspend()
821 ret = clk_prepare_enable(ctx->vclk); in exynos7_decon_resume()
823 DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n", in exynos7_decon_resume()
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| /Linux-v6.1/drivers/gpu/drm/nouveau/dispnv04/ |
| D | arb.c | 193 nv04_update_arb(struct drm_device *dev, int VClk, int bpp, in nv04_update_arb() argument
205 sim_data.pclk_khz = VClk; in nv04_update_arb()
252 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) in nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); in nouveau_calc_arb()
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| /Linux-v6.1/drivers/video/fbdev/via/ |
| D | vt1636.c | 186 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3324()
210 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3327()
227 index = get_clk_range_index(plvds_setting_info->vclk); in viafb_vt1636_patch_skew_on_vt3364()
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| /Linux-v6.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| D | smu_v13_0_5_ppsmc.h | 52 #define PPSMC_MSG_SetSoftMaxVcn 17 ///< Set soft max for VCN clocks (VCLK and DCLK)
59 #define PPSMC_MSG_SetSoftMinVcn 24 ///< Set soft min for VCN clocks (VCLK and DCLK)
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| D | smu_v13_0_1_ppsmc.h | 65 #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCL…
75 #define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCL…
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| /Linux-v6.1/drivers/video/fbdev/riva/ |
| D | riva_hw.c | 609 unsigned VClk, in nv3UpdateArbitrationSettings() argument
635 sim_data.pclk_khz = VClk; in nv3UpdateArbitrationSettings()
793 unsigned VClk, in nv4UpdateArbitrationSettings() argument
820 sim_data.pclk_khz = VClk; in nv4UpdateArbitrationSettings()
1042 unsigned VClk, in nv10UpdateArbitrationSettings() argument
1071 sim_data.pclk_khz = VClk; in nv10UpdateArbitrationSettings()
1087 unsigned VClk, in nForceUpdateArbitrationSettings() argument
1127 sim_data.pclk_khz = VClk; in nForceUpdateArbitrationSettings()
1162 unsigned VClk, Freq; in CalcVClock() local
1167 VClk = (unsigned)clockIn; in CalcVClock()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| D | power_state.h | 143 uint32_t VCLK; member
183 unsigned long vclk; member
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | dcn301_smu.h | 38 uint32_t vclk; member
120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
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| /Linux-v6.1/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 73 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
90 * - Generate the pixel clock for the LCD monitor (instead of VCLK)
216 printk(KERN_CRIT "atyfb: vclk out of range\n"); in aty_valid_pll_ct()
229 printk("atyfb(%s): pllvclk=%d MHz, vclk=%d MHz\n", in aty_valid_pll_ct()
232 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */ in aty_valid_pll_ct()
314 /* Reset VCLK generator */ in aty_set_pll_ct()
337 /* End VCLK generator reset */ in aty_set_pll_ct()
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| /Linux-v6.1/Documentation/devicetree/bindings/display/ |
| D | xylon,logicvc-display.yaml | 45 # vclk is required and must be provided as first item.
46 - const: vclk
228 clock-names = "vclk", "lvdsclk";
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| D | amlogic,meson-vpu.yaml | 20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
53 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
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| /Linux-v6.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu8_hwmgr.c | 140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; in smu8_upload_pptable_to_smu()
597 clock = table->entries[level].vclk; in smu8_init_uvd_limit()
599 clock = table->entries[table->count - 1].vclk; in smu8_init_uvd_limit()
1415 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; in smu8_dpm_get_pp_table_entry()
1723 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1757 vclk = uvd_table->entries[uvd_index].vclk; in smu8_read_sensor()
1758 *((uint32_t *)value) = vclk; in smu8_read_sensor()
1893 ptable->entries[ptable->count - 1].vclk; in smu8_dpm_update_uvd_dpm()
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| /Linux-v6.1/drivers/video/fbdev/sis/ |
| D | init.c | 2021 /* RESET VCLK */
2173 /* VCLK */
2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2272 unsigned int longtemp = VCLK * colordepth; in SiS_DoCalcDelay()
2288 SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK, in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2311 /* Get VCLK */ in SiS_SetCRT1FIFO_300()
2313 VCLK = SiS_Pr->CSRClock; in SiS_SetCRT1FIFO_300()
[all …]
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| /Linux-v6.1/drivers/usb/misc/sisusbvga/ |
| D | sisusb_init.c | 582 /* VCLK */
633 unsigned short data = 0, VCLK = 0, index = 0; in SiS_SetVCLKState() local
637 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK; in SiS_SetVCLKState()
640 if (VCLK >= 166) in SiS_SetVCLKState()
644 if (VCLK >= 166) in SiS_SetVCLKState()
649 if (VCLK >= 260) in SiS_SetVCLKState()
651 else if (VCLK >= 160) in SiS_SetVCLKState()
653 else if (VCLK >= 135) in SiS_SetVCLKState()
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| /Linux-v6.1/drivers/gpu/drm/logicvc/ |
| D | logicvc_drm.c | 156 .clk = &logicvc->vclk, in logicvc_clocks_prepare()
157 .name = "vclk", in logicvc_clocks_prepare()
222 &logicvc->vclk, in logicvc_clocks_unprepare()
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| /Linux-v6.1/drivers/gpu/drm/meson/ |
| D | meson_vclk.c | 18 * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
34 * | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
39 * Final clocks can take input for either VCLK or VCLK2, but
40 * VCLK is the preferred path for HDMI clocking and VCLK2 is the
43 * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
884 /* Set VCLK div */ in meson_vclk_set()
1101 pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq); in meson_vclk_setup()
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