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/Linux-v6.1/tools/perf/pmu-events/arch/arm64/
Drecommended.json69 "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
75 "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
123 "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
129 "PublicDescription": "Attributable Level 2 data or unified TLB refill, write",
135 "PublicDescription": "Attributable Level 2 data or unified TLB access, read",
141 "PublicDescription": "Attributable Level 2 data or unified TLB access, write",
411 "PublicDescription": "Attributable Level 3 data or unified cache access, read",
414 "BriefDescription": "Attributable Level 3 data or unified cache access, read"
417 "PublicDescription": "Attributable Level 3 data or unified cache access, write",
420 "BriefDescription": "Attributable Level 3 data or unified cache access, write"
[all …]
Dcommon-and-microarch.json219 "PublicDescription": "Attributable Level 1 data or unified TLB access",
222 "BriefDescription": "Attributable Level 1 data or unified TLB access"
261 "PublicDescription": "Attributable Level 2 data or unified TLB access",
264 "BriefDescription": "Attributable Level 2 data or unified TLB access"
309 …itional latency because it returns data from outside the Level 1 data or unified cache of this pro…
393unified cache of this processing element. The event indicates to software that the access missed …
399unified cache of this processing element. The event indicates to software that the access missed …
/Linux-v6.1/arch/arm/include/asm/
Dunified.h3 * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
12 .syntax unified
14 __asm__(".syntax unified");
/Linux-v6.1/Documentation/devicetree/bindings/arm/socionext/
Dsocionext,uniphier-system-cache.yaml35 cache-unified: true
58 - cache-unified
71 cache-unified;
84 cache-unified;
96 cache-unified;
/Linux-v6.1/drivers/misc/habanalabs/common/
Dmemory_mgr.c14 * @mmg: parent unified memory manager
107 * @mmg: parent unified memory manager
140 * @mmg: parent unified memory manager
225 * @mmg: unified memory manager
308 * hl_mem_mgr_init - initialize unified memory manager
313 * Initialize an instance of unified memory manager
323 * hl_mem_mgr_fini - release unified memory manager
325 * @mmg: parent unified memory manager
327 * Release the unified memory manager. Shall be called from an interrupt context.
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z10/
Dbasic.json21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z13/
Dbasic.json21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z196/
Dbasic.json21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_zec12/
Dbasic.json21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
63 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
70 …unts the total number of penalty cycles for level-1 instruction cache or unified cache while the C…
/Linux-v6.1/arch/arm64/boot/dts/amd/
Damd-seattle-cpus.dtsi169 cache-unified;
177 cache-unified;
185 cache-unified;
193 cache-unified;
202 cache-unified;
/Linux-v6.1/arch/m68k/include/asm/
Dm53xxacr.h17 * cache setup. They have a unified instruction and data cache, with
56 #define CACHE_SIZE 0x2000 /* 8k of unified cache */
60 #define CACHE_SIZE 0x4000 /* 16k of unified cache */
87 * Unified cache means we will never need to flush for coherency of
/Linux-v6.1/drivers/connector/
DKconfig4 tristate "Connector - unified userspace <-> kernelspace linker"
7 This is unified userspace <-> kernelspace connector working on top
/Linux-v6.1/Documentation/devicetree/bindings/riscv/
Dsifive,ccache0.yaml58 cache-unified: true
144 - cache-unified
156 cache-unified;
/Linux-v6.1/arch/arm/kernel/
Dhead-nommu.S223 /* Setup a single MPU region, either D or I side (D-side for unified) */
281 /* Determine whether the D/I-side memory map is unified. We set the
287 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
297 beq 1f @ Memory-map not unified
310 beq 2f @ Memory-map not unified
329 beq 3f @ Memory-map not unified
473 /* Determine whether the D/I-side memory map is unified. We set the
485 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
/Linux-v6.1/arch/arm/mm/
Dcache-v6.S179 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
211 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
222 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
228 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
255 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
Dpmsa-v7.c52 /* Data-side / unified region attributes */
108 /* Data-side / unified region attributes */
137 /* ARMv7-M only supports a unified MPU, so I-side operations are nop */
336 /* MPUIR.nU specifies whether there is *not* a unified memory map */ in mpu_iside_independent()
354 /* If the MPU is non-unified, we use the larger of the two minima*/ in __mpu_min_region_order()
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/
Dcache.json64 "BriefDescription": "Attributable Level 3 unified cache refill."
69 "BriefDescription": "Attributable Level 3 unified cache access."
74 "BriefDescription": "Attributable L2 data or unified TLB refill"
/Linux-v6.1/Documentation/misc-devices/
Duacce.rst6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
11 Because of the unified address, hardware and user space of process can
51 FIFO-like interface. And it maintains a unified address space between the
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z16/
Dbasic.json21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z14/
Dbasic.json21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
/Linux-v6.1/tools/perf/pmu-events/arch/s390/cf_z15/
Dbasic.json21 …": "This counter counts the total number of level-1 instruction-cache or unified-cache directory w…
28 …er counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
/Linux-v6.1/include/linux/mtd/
Dflashchip.h39 /* These 2 come from nand_state_t, which has been unified here */
42 /* These 4 come from onenand_state_t, which has been unified here */
/Linux-v6.1/drivers/gpu/drm/amd/amdkfd/
Dkfd_flat_memory.c57 * System Unified Address - SUA
70 * system unified address (SUA).
91 * unified address” feature (SUA) is the mapping of GPUVM and ATC address
92 * spaces into a unified pointer space. The method we take for 64b mode is
206 * Device Unified Address - DUA
208 * Device unified address (DUA) is the name of the feature that maps the
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
Dcache.json159 …"PublicDescription": "Prefetch access to unified TLB that caused a page table walk. This event cou…
162 …"BriefDescription": "Prefetch access to unified TLB that caused a page table walk. This event coun…
/Linux-v6.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
Dcache.json219 …"PublicDescription": "Unattributable Level 3 data or unified cache allocation without refill. This…
222 …"BriefDescription": "Unattributable Level 3 data or unified cache allocation without refill. This …
225 …"PublicDescription": "Unattributable Level 3 data or unified cache refill. This event occurs when …
228 …"BriefDescription": "Unattributable Level 3 data or unified cache refill. This event occurs when a…

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