Searched full:ultrascale (Results 1 – 25 of 28) sorted by relevance
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| /Linux-v5.10/Documentation/devicetree/bindings/reset/ |
| D | xlnx,zynqmp-reset.txt | 2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
41 For list of all valid reset indices for Zynq UltraScale+ MPSoC see
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | xlnx,zynqmp-clk.txt | 2 Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
5 The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
22 Input clocks for zynqmp Ultrascale+ clock controller:
24 The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
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| /Linux-v5.10/arch/microblaze/kernel/cpu/ |
| D | cpuinfo.c | 79 {"UltraScale Virtex", 0x13},
80 {"UltraScale Kintex", 0x14},
81 {"UltraScale+ Zynq", 0x15},
82 {"UltraScale+ Virtex", 0x16},
83 {"UltraScale+ Kintex", 0x17},
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| /Linux-v5.10/drivers/clk/zynqmp/ |
| D | Kconfig | 4 bool "Support for Xilinx ZynqMP Ultrascale+ clock controllers"
8 Support for the Zynqmp Ultrascale clock controller.
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| D | Makefile | 2 # Zynq Ultrascale+ MPSoC clock specific Makefile
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| D | clk-gate-zynqmp.c | 3 * Zynq UltraScale+ MPSoC clock controller
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| D | clk-mux-zynqmp.c | 3 * Zynq UltraScale+ MPSoC mux
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| D | clkc.c | 3 * Zynq UltraScale+ MPSoC clock controller
647 pr_err("Zynq Ultrascale+ MPSoC clk %s: register failed with %ld\n", in zynqmp_register_clocks()
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| D | pll.c | 3 * Zynq UltraScale+ MPSoC PLL driver
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| D | divider.c | 3 * Zynq UltraScale+ MPSoC Divider support
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| /Linux-v5.10/Documentation/devicetree/bindings/firmware/xilinx/ |
| D | xlnx,zynqmp-firmware.txt | 15 "xlnx,zynqmp-firmware" for Zynq Ultrascale+ MPSoC
26 Zynq Ultrascale+ MPSoC
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| /Linux-v5.10/Documentation/devicetree/bindings/display/xlnx/ |
| D | xlnx,zynqmp-dpsub.yaml | 10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
40 Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
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| /Linux-v5.10/Documentation/devicetree/bindings/fpga/ |
| D | xlnx,zynqmp-pcap-fpga.txt | 1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
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| /Linux-v5.10/Documentation/devicetree/bindings/rtc/ |
| D | xlnx-rtc.txt | 1 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
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| /Linux-v5.10/Documentation/devicetree/bindings/serial/ |
| D | cdns,uart.txt | 6 Use "xlnx,zynqmp-uart","cdns,uart-r1p12" for Zynq Ultrascale+ MPSoC.
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| /Linux-v5.10/Documentation/devicetree/bindings/spi/ |
| D | spi-zynqmp-qspi.txt | 1 Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
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| /Linux-v5.10/Documentation/misc-devices/ |
| D | xilinx_sdfec.rst | 10 This driver supports SD-FEC Integrated Block for Zynq |Ultrascale+ (TM)| RFSoCs.
12 .. |Ultrascale+ (TM)| unicode:: Ultrascale+ U+2122
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| /Linux-v5.10/Documentation/devicetree/bindings/nvmem/ |
| D | xlnx,zynqmp-nvmem.txt | 2 = Zynq UltraScale+ MPSoC nvmem firmware driver binding =
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| /Linux-v5.10/Documentation/devicetree/bindings/net/ |
| D | macb.txt | 17 Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | xilinx.yaml | 13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
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| /Linux-v5.10/Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.txt | 5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
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| /Linux-v5.10/drivers/rtc/ |
| D | rtc-zynqmp.c | 3 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
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| D | Kconfig | 1298 tristate "Xilinx Zynq Ultrascale+ MPSoC RTC"
1302 Xilinx Zynq Ultrascale+ MPSoC.
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| /Linux-v5.10/drivers/mtd/nand/raw/ |
| D | Kconfig | 463 Zynq Ultrascale+ MPSoC.
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| /Linux-v5.10/drivers/ata/ |
| D | Kconfig | 203 It can be found on the Xilinx Zynq UltraScale+ MPSoC.
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