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/Linux-v5.10/drivers/media/pci/ivtv/
Divtv-udma.c12 #include "ivtv-udma.h"
82 if (itv->udma.SG_handle == 0) { in ivtv_udma_alloc()
84 itv->udma.SG_handle = pci_map_single(itv->pdev, itv->udma.SGarray, in ivtv_udma_alloc()
85 sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE); in ivtv_udma_alloc()
94 struct ivtv_user_dma *dma = &itv->udma; in ivtv_udma_setup()
152 struct ivtv_user_dma *dma = &itv->udma; in ivtv_udma_unmap()
177 if (itv->udma.SG_handle) { in ivtv_udma_free()
178 pci_unmap_single(itv->pdev, itv->udma.SG_handle, in ivtv_udma_free()
179 sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE); in ivtv_udma_free()
183 if (itv->udma.SG_length) { in ivtv_udma_free()
[all …]
Divtv-udma.h26 pci_dma_sync_single_for_device(itv->pdev, itv->udma.SG_handle, in ivtv_udma_sync_for_device()
27 sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE); in ivtv_udma_sync_for_device()
32 pci_dma_sync_single_for_cpu(itv->pdev, itv->udma.SG_handle, in ivtv_udma_sync_for_cpu()
33 sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE); in ivtv_udma_sync_for_cpu()
/Linux-v5.10/Documentation/devicetree/bindings/dma/ti/
Dk3-udma.yaml4 $id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
13 The UDMA-P is intended to perform similar (but significantly upgraded)
14 functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
16 The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
29 The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
30 channels. Channels in the UDMA-P can be configured to be either Packet-Based
35 The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
93 Array of UDMA tchan resource subtypes for resource allocation for this
102 Array of UDMA rchan resource subtypes for resource allocation for this
111 Array of UDMA rflow resource subtypes for resource allocation for this
[all …]
/Linux-v5.10/drivers/ata/
Dpata_amd.c77 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1; in timing_setup()
78 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15; in timing_setup()
99 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03; in timing_setup()
103 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03; in timing_setup()
107 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03; in timing_setup()
111 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03; in timing_setup()
118 /* UDMA timing */ in timing_setup()
119 if (at.udma) in timing_setup()
238 * Program the MWDMA/UDMA modes for the AMD and Nvidia
276 u32 saved_udma, udma; in nv_mode_filter() local
[all …]
Dpata_via.c13 * VIA VT82C586a - Added UDMA to 33Mhz
195 /* UDMA 66 chips have only drive side logic */ in via_cable_detect()
198 /* UDMA 100 or later */ in via_cable_detect()
236 * @udma_type: UDMA mode/format of registers
294 /* Load the UDMA bits according to type */ in via_do_set_mode()
298 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; in via_do_set_mode()
301 ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; in via_do_set_mode()
304 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; in via_do_set_mode()
307 ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; in via_do_set_mode()
311 /* Set UDMA unless device is not UDMA capable */ in via_do_set_mode()
[all …]
Dpata_serverworks.c20 * supports UDMA mode 2 (33 MB/s)
23 * all revisions support UDMA mode 4 (66 MB/s)
24 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
49 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
149 * specific rules. OSB4 requires no UDMA for disks due to a FIFO
175 /* Disk, UDMA */ in serverworks_csb_filter()
222 * Program the MWDMA/UDMA modes for the serverworks OSB4/CSB5
224 * while the chipset uses mode number for UDMA.
288 printk(KERN_DEBUG DRV_NAME ": UDMA not BIOS enabled.\n"); in serverworks_fixup_osb4()
289 reg |= 0x00004000; /* enable UDMA/33 support */ in serverworks_fixup_osb4()
[all …]
Dpata_it821x.c60 * non UDMA devices restrict each others performance. It also has a
95 u16 udma[2]; /* Cached UDMA values (per drive) */ member
143 * it821x_program_udma - program the UDMA registers
148 * Program the UDMA timing for this drive according to the
150 * the errata on the 0x10 revision. The UDMA errata is partly handled
162 /* Program UDMA timing bits */ in it821x_program_udma()
229 * Reprogram the UDMA/PIO of the pair drive for the switch in it821x_clock_strategy()
232 if (pair && itdev->udma[1-unit] != UDMA_OFF) { in it821x_clock_strategy()
233 it821x_program_udma(ap, pair, itdev->udma[1-unit]); in it821x_clock_strategy()
237 * Reprogram the UDMA/PIO of our drive for the switch. in it821x_clock_strategy()
[all …]
Dpata_artop.c93 * matching PIO clocking for UDMA, as well as the MWDMA timings.
118 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
119 * the event UDMA is used the later call to set_dmamode will set the
134 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ in artop6210_set_piomode()
172 * ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
173 * the event UDMA is used the later call to set_dmamode will set the
187 /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */ in artop6260_set_piomode()
222 /* Add ultra DMA bits if in UDMA mode */ in artop6210_set_dmamode()
258 /* Add ultra DMA bits if in UDMA mode */ in artop6260_set_dmamode()
319 /* BIOS may have left us in UDMA, clear it before libata probe */ in atp8xx_fixup()
Dpata_rdc.c149 /* Ensure the UDMA bit is off - it will be turned back on if in rdc_set_piomode()
150 UDMA is selected */ in rdc_set_piomode()
164 * Set UDMA mode for device, in host controller PCI config space.
193 unsigned int udma = adev->dma_mode - XFER_UDMA_0; in rdc_set_dmamode() local
199 * UDMA is handled by a combination of clock switching and in rdc_set_dmamode()
205 u_speed = min(2 - (udma & 1), udma); in rdc_set_dmamode()
206 if (udma == 5) in rdc_set_dmamode()
208 else if (udma > 2) in rdc_set_dmamode()
Dpata_ali.c115 * fix that later on. Also ensure we do not do UDMA on WDC drives
163 * @ultra: UDMA timing or zero for off
165 * Loads the timing registers for cmd/data and disable UDMA if
166 * ultra is zero. If ultra is set then load and enable the UDMA
176 int udmat = 0x56 + ap->port_no; /* UDMA timing */ in ali_program_modes()
178 u8 udma; in ali_program_modes() local
192 /* Set up the UDMA enable */ in ali_program_modes()
193 pci_read_config_byte(pdev, udmat, &udma); in ali_program_modes()
194 udma &= ~(0x0F << shift); in ali_program_modes()
195 udma |= ultra << shift; in ali_program_modes()
[all …]
Dpata_pdc2027x.c100 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
101 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
102 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
103 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
104 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
105 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
106 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
258 * Block UDMA on devices that cause trouble with this controller.
272 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */ in pdc2027x_mode_filter()
324 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
[all …]
Dlibata-pata-timings.c18 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
71 q->udma = EZ(t->udma, UT); in ata_timing_quantize()
94 m->udma = max(a->udma, b->udma); in ata_timing_merge()
158 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, in ata_timing_compute()
Dpata_bk3710.c59 { 160, 240 / 2 }, /* UDMA Mode 0 */
60 { 125, 160 / 2 }, /* UDMA Mode 1 */
61 { 100, 120 / 2 }, /* UDMA Mode 2 */
62 { 100, 90 / 2 }, /* UDMA Mode 3 */
63 { 100, 60 / 2 }, /* UDMA Mode 4 */
64 { 85, 40 / 2 }, /* UDMA Mode 5 */
96 /* Enable UDMA for Device */ in pata_bk3710_setudmamode()
128 /* Disable UDMA for Device */ in pata_bk3710_setmwdmamode()
Dpata_atiixp.c52 u8 udma; in atiixp_cable_detect() local
59 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); in atiixp_cable_detect()
60 if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40) in atiixp_cable_detect()
204 * When DMA begins we need to ensure that the UDMA control
233 * DMA has completed. Clear the UDMA flag as the next operations will
234 * be PIO ones not UDMA data transfer.
Dpata_it8213.c133 * Set UDMA/MWDMA mode for device, in host controller PCI config space.
159 unsigned int udma = adev->dma_mode - XFER_UDMA_0; in it8213_set_dmamode() local
165 u_speed = min(2 - (udma & 1), udma); in it8213_set_dmamode()
166 if (udma > 4) in it8213_set_dmamode()
168 else if (udma > 2) in it8213_set_dmamode()
175 /* Load the UDMA cycle time */ in it8213_set_dmamode()
Dpata_hpt3x3.c33 * all we have to do is clear the MWDMA and UDMA bits then load the
48 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */ in hpt3x3_set_piomode()
60 * Set up the channel for MWDMA or UDMA modes. Much the same as with
61 * PIO, load the mode number and then set MWDMA or UDMA flag.
64 * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
79 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */ in hpt3x3_set_dmamode()
/Linux-v5.10/drivers/ide/
Damd74xx.c62 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; in amd_set_speed()
63 …case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; b… in amd_set_speed()
64 …case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; b… in amd_set_speed()
65 …case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; b… in amd_set_speed()
69 if (timing->udma) in amd_set_speed()
97 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1; in amd_set_drive()
98 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15; in amd_set_drive()
151 ; /* no UDMA > 2 */ in init_chipset_amd74xx()
196 #define DECLARE_AMD_DEV(swdma, udma) \ argument
206 .udma_mask = udma, \
[all …]
Dit821x.c49 * non UDMA devices restrict each others performance. It also has a
57 * - ATAPI UDMA is ok but not MWDMA it seems
83 u16 udma[2]; /* Cached UDMA values (per drive) */ member
130 * it821x_program_udma - program the UDMA registers
134 * Program the UDMA timing for this drive according to the
146 /* Program UDMA timing bits */ in it821x_program_udma()
213 * Reprogram the UDMA/PIO of the pair drive for the switch in it821x_clock_strategy()
216 if(pair && itdev->udma[1-unit] != UDMA_OFF) { in it821x_clock_strategy()
217 it821x_program_udma(pair, itdev->udma[1-unit]); in it821x_clock_strategy()
221 * Reprogram the UDMA/PIO of our drive for the switch. in it821x_clock_strategy()
[all …]
Dvia82cxxx.c141 case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; in via_set_speed()
142 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; in via_set_speed()
143 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; in via_set_speed()
144 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; in via_set_speed()
147 /* Set UDMA unless device is not UDMA capable */ in via_set_speed()
156 if (timing->udma) { in via_set_speed()
252 * UDMA w/ < 3T/cycle in via_cable_detect()
264 * UDMA w/ < 60ns/cycle in via_cable_detect()
276 * UDMA w/ < 60ns/cycle in via_cable_detect()
Dide-xfer-mode.c11 { "UDMA/16", "UDMA/25", "UDMA/33", "UDMA/44",
12 "UDMA/66", "UDMA/100", "UDMA/133", "UDMA7" };
Dide-timings.c16 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
106 q->udma = EZ(t->udma, UT); in ide_timing_quantize()
127 m->udma = max(a->udma, b->udma); in ide_timing_merge()
174 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, in ide_timing_compute()
Dcs5530.c63 * cs5530_udma_filter - UDMA filter
66 * cs5530_udma_filter() does UDMA mask filtering for the given drive
70 * UDMA/MDMA. It has to be one or the other, for the pair, though
77 * Note: This relies on the fact we never fail from UDMA to MWDMA2
123 reg |= 0x00100000; /* enable UDMA timings for both drives */ in cs5530_set_dma_mode()
125 reg &= ~0x00100000; /* disable UDMA timings for both drives */ in cs5530_set_dma_mode()
181 * Disable trapping of UDMA register accesses (Win98 hack): in init_chipset_cs5530()
Dpiix.c24 * PIIX4 errata #10 - BM IDE hang with non UDMA
36 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
159 u8 udma = speed - XFER_UDMA_0; in piix_set_dma_mode() local
161 u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4); in piix_set_dma_mode()
322 #define DECLARE_PIIX_DEV(udma) \ argument
331 .udma_mask = udma, \
334 #define DECLARE_ICH_DEV(mwdma, udma) \ argument
344 .udma_mask = udma, \
361 DECLARE_PIIX_DEV(0x00), /* no udma */
/Linux-v5.10/Documentation/devicetree/bindings/ata/
Dpata-arasan.txt21 - arasan,broken-udma: if present, UDMA mode is unusable
25 required unless both UDMA and MWDMA mode are broken
/Linux-v5.10/drivers/dma/ti/
DKconfig38 bool "Texas Instruments UDMA support"
47 Enable support for the TI UDMA (Unified DMA) controller. This
51 bool "Texas Instruments UDMA Glue layer for non DMAengine users"

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