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/Linux-v5.4/sound/drivers/
Dserial-u16550.c159 static inline void snd_uart16550_add_timer(struct snd_uart16550 *uart) in snd_uart16550_add_timer() argument
161 if (!uart->timer_running) { in snd_uart16550_add_timer()
163 mod_timer(&uart->buffer_timer, jiffies + (HZ + 255) / 256); in snd_uart16550_add_timer()
164 uart->timer_running = 1; in snd_uart16550_add_timer()
168 static inline void snd_uart16550_del_timer(struct snd_uart16550 *uart) in snd_uart16550_del_timer() argument
170 if (uart->timer_running) { in snd_uart16550_del_timer()
171 del_timer(&uart->buffer_timer); in snd_uart16550_del_timer()
172 uart->timer_running = 0; in snd_uart16550_del_timer()
177 static inline void snd_uart16550_buffer_output(struct snd_uart16550 *uart) in snd_uart16550_buffer_output() argument
179 unsigned short buff_out = uart->buff_out; in snd_uart16550_buffer_output()
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/Linux-v5.4/Documentation/devicetree/bindings/serial/
Drenesas,sci-serial.txt7 - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
8 - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
9 - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
10 - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
11 - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
12 - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
13 - "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
14 - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
15 - "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
16 - "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART.
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Dmvebu-uart.txt1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
20 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
21 respectively the UART sum interrupt, the UART TX interrupt and
22 UART RX interrupt. A corresponding interrupt-names property must
25 (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx",
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Dmtk-uart.txt1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
13 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
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Dsnps-dw-apb-uart.yaml4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
22 - const: renesas,rzn1-uart
25 - rockchip,px30-uart
26 - rockchip,rk3036-uart
27 - rockchip,rk3066-uart
28 - rockchip,rk3188-uart
29 - rockchip,rk3288-uart
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Dsirf-uart.txt4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
7 - interrupts : Should contain uart interrupt
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
20 compatible = "sirf,prima2-uart";
30 compatible = "sirf,prima2-usp-uart";
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D8250.txt1 * UART (Universal Asynchronous Receiver/Transmitter)
11 - For Tegra20, must contain "nvidia,tegra20-uart"
12 - For other Tegra, must contain '"nvidia,<chip>-uart",
13 "nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
15 - "nxp,lpc3220-uart"
16 - "ralink,rt2880-uart"
24 - "intel,xscale-uart"
25 - "ti,da830-uart"
28 - "nuvoton,npcm750-uart"
31 - interrupts : should contain uart interrupt.
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Damlogic,meson-uart.yaml5 $id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
25 - description: Always-on power domain UART controller
28 - amlogic,meson6-uart
29 - amlogic,meson8-uart
30 - amlogic,meson8b-uart
31 - amlogic,meson-gx-uart
32 - const: amlogic,meson-ao-uart
33 - description: Everything-Else power domain UART controller
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Domap_serial.txt1 OMAP UART controller
4 - compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
5 - compatible : should be "ti,am654-uart" for AM654 controllers
6 - compatible : should be "ti,omap2-uart" for OMAP2 controllers
7 - compatible : should be "ti,omap3-uart" for OMAP3 controllers
8 - compatible : should be "ti,omap4-uart" for OMAP4 controllers
9 - compatible : should be "ti,am4372-uart" for AM437x controllers
10 - compatible : should be "ti,am3352-uart" for AM335x controllers
11 - compatible : should be "ti,dra742-uart" for DRA7x controllers
13 - interrupts or interrupts-extended : Should contain the uart interrupt
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Dsamsung_uart.txt1 * Samsung's UART Controller
3 The Samsung's UART controller is used for interfacing SoC with serial
8 - "samsung,exynos4210-uart" - Exynos4210 SoC,
9 - "samsung,s3c2410-uart" - compatible with ports present on S3C2410 SoC,
10 - "samsung,s3c2412-uart" - compatible with ports present on S3C2412 SoC,
11 - "samsung,s3c2440-uart" - compatible with ports present on S3C2440 SoC,
12 - "samsung,s3c6400-uart" - compatible with ports present on S3C6400 SoC,
13 - "samsung,s5pv210-uart" - compatible with ports present on S5PV210 SoC.
22 - "uart" - controller bus clock,
33 - samsung,uart-fifosize: The fifo size supported by the UART channel
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Dsprd-uart.txt1 * Spreadtrum serial UART
5 * "sprd,sc9836-uart"
6 * "sprd,sc9860-uart", "sprd,sc9836-uart"
11 "enable" for UART module enable clock,
12 "uart" for UART clock,
13 "source" for UART source (parent) clock.
15 UART clock and source clock are optional properties, but enable clock
24 compatible = "sprd,sc9860-uart",
25 "sprd,sc9836-uart";
30 clock-names = "enable", "uart", "source";
/Linux-v5.4/drivers/tty/serial/
Dmen_z135_uart.c3 * MEN 16z135 High Speed UART
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
149 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_set()
154 * @uart: The UART port
158 static void men_z135_reg_clr(struct men_z135_port *uart, in men_z135_reg_clr() argument
161 struct uart_port *port = &uart->port; in men_z135_reg_clr()
165 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_clr()
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Dtimbuart.c3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
55 struct timbuart_port *uart = in timbuart_start_tx() local
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
121 struct timbuart_port *uart = in timbuart_handle_tx_port() local
140 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
177 struct timbuart_port *uart = (struct timbuart_port *)arg; in timbuart_tasklet() local
180 spin_lock(&uart->port.lock); in timbuart_tasklet()
182 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
183 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
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Darc_uart.c3 * ARC On-Chip(fpga) UART Driver
17 * -New Serial Core based ARC UART driver
41 * ARC UART Hardware Specs
46 * UART Register set (this is not a Standards Compliant IP)
58 /* Bits for UART Status Reg (R/W) */
71 /* Uart bit fiddling helpers: lowest level */
79 /* Uart bit fiddling helpers: API level */
80 #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val) argument
81 #define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA) argument
83 #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val) argument
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/Linux-v5.4/arch/mips/kernel/
Dcps-vec-ns16550.S18 * _mips_cps_putc() - write a character to the UART
20 * @t9: UART base address
31 * _mips_cps_puts() - write a string to the UART
33 * @t9: UART base address
35 * Write a null-terminated ASCII string to the UART.
51 * _mips_cps_putx4 - write a 4b hex value to the UART
52 * @a0: the 4b value to write to the UART
53 * @t9: UART base address
55 * Write a single hexadecimal character to the UART.
68 * _mips_cps_putx8 - write an 8b hex value to the UART
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/Linux-v5.4/arch/arm/include/debug/
Dtegra.S45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
60 /* If clear, can't use UART; jump to save no UART */ \
62 /* Passed all tests, load address of UART registers */ \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
64 /* Jump to save UART address */ \
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
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/Linux-v5.4/include/uapi/linux/
Dserial_core.h45 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
46 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
47 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
48 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
49 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
50 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
51 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
55 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
56 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
57 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
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/Linux-v5.4/drivers/tty/serial/8250/
D8250_core.c287 * IIR bits on their UART, but it's specifically designed for in serial8250_backup_timeout()
288 * the "Diva" UART used on the management processor on many HP in serial8250_backup_timeout()
596 * Check whether an invalid uart number has been specified, and in univ8250_console_setup()
620 * console=uart[8250],io|mmio|mmio16|mmio32,<addr>[,<options>]
621 * console=uart[8250],0x<addr>[,<options>]
633 char match[] = "uart"; /* 8250-specific earlycon name */ in univ8250_console_match()
800 struct uart_8250_port uart; in serial8250_probe() local
803 memset(&uart, 0, sizeof(uart)); in serial8250_probe()
809 uart.port.iobase = p->iobase; in serial8250_probe()
810 uart.port.membase = p->membase; in serial8250_probe()
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D8250_lpc18xx.c3 * Serial port driver for NXP LPC18xx/43xx UART
104 struct uart_8250_port uart; in lpc18xx_serial_probe() local
118 memset(&uart, 0, sizeof(uart)); in lpc18xx_serial_probe()
120 uart.port.membase = devm_ioremap(&pdev->dev, res->start, in lpc18xx_serial_probe()
122 if (!uart.port.membase) in lpc18xx_serial_probe()
131 dev_err(&pdev->dev, "uart clock not found\n"); in lpc18xx_serial_probe()
149 dev_err(&pdev->dev, "unable to enable uart clock\n"); in lpc18xx_serial_probe()
155 uart.port.line = ret; in lpc18xx_serial_probe()
160 spin_lock_init(&uart.port.lock); in lpc18xx_serial_probe()
161 uart.port.dev = &pdev->dev; in lpc18xx_serial_probe()
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D8250_bcm2835aux.c3 * Serial port driver for BCM2835AUX UART
20 struct uart_8250_port uart; member
37 spin_lock_init(&data->uart.port.lock); in bcm2835aux_serial_probe()
38 data->uart.capabilities = UART_CAP_FIFO | UART_CAP_MINI; in bcm2835aux_serial_probe()
39 data->uart.port.dev = &pdev->dev; in bcm2835aux_serial_probe()
40 data->uart.port.regshift = 2; in bcm2835aux_serial_probe()
41 data->uart.port.type = PORT_16550; in bcm2835aux_serial_probe()
42 data->uart.port.iotype = UPIO_MEM; in bcm2835aux_serial_probe()
43 data->uart.port.fifosize = 8; in bcm2835aux_serial_probe()
44 data->uart.port.flags = UPF_SHARE_IRQ | in bcm2835aux_serial_probe()
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D8250_ingenic.c6 * Ingenic SoC UART support
132 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
135 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
144 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
153 /* UART module enable */ in ingenic_uart_serial_out()
209 struct uart_8250_port uart = {}; in ingenic_uart_probe() local
233 spin_lock_init(&uart.port.lock); in ingenic_uart_probe()
234 uart.port.type = PORT_16550A; in ingenic_uart_probe()
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D8250_pxa.c58 { .compatible = "mrvl,pxa-uart", },
59 { .compatible = "mrvl,mmp-uart", },
64 /* Uart divisor latch write */
94 struct uart_8250_port uart = {}; in serial_pxa_probe() local
118 uart.port.line = ret; in serial_pxa_probe()
120 uart.port.type = PORT_XSCALE; in serial_pxa_probe()
121 uart.port.iotype = UPIO_MEM32; in serial_pxa_probe()
122 uart.port.mapbase = mmres->start; in serial_pxa_probe()
123 uart.port.regshift = 2; in serial_pxa_probe()
124 uart.port.irq = irqres->start; in serial_pxa_probe()
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D8250_hp300.c63 /* Offset to UART registers from base of DCA */
160 struct uart_8250_port uart; in hpdca_init_one() local
169 memset(&uart, 0, sizeof(uart)); in hpdca_init_one()
172 uart.port.iotype = UPIO_MEM; in hpdca_init_one()
173 uart.port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF; in hpdca_init_one()
174 uart.port.irq = d->ipl; in hpdca_init_one()
175 uart.port.uartclk = HPDCA_BAUD_BASE * 16; in hpdca_init_one()
176 uart.port.mapbase = (d->resource.start + UART_OFFSET); in hpdca_init_one()
177 uart.port.membase = (char *)(uart.port.mapbase + DIO_VIRADDRBASE); in hpdca_init_one()
178 uart.port.regshift = 1; in hpdca_init_one()
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/Linux-v5.4/arch/arm/
DKconfig.debug112 UART definition, as specified below. Attempting to boot the kernel
129 bool "Kernel low-level debugging via asm9260 UART"
133 their output to an UART or USART port on asm9260 based
195 bool "Kernel low-level debugging on BCM2835 PL011 UART"
200 bool "Kernel low-level debugging on BCM2836 PL011 UART"
223 bool "Kernel low-level debugging messages via BCM KONA UART"
234 bool "Kernel low-level debugging on BCM63XX UART"
238 bool "Marvell Berlin SoC Debug UART"
246 bool "Use BRCMSTB UART for low-level debug"
251 UART physical and virtual address is automatically provided
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/Linux-v5.4/drivers/firmware/
Dpcdp.c20 setup_serial_console(struct pcdp_uart *uart) in setup_serial_console() argument
27 mmio = (uart->addr.space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY); in setup_serial_console()
29 mmio ? "mmio" : "io", uart->addr.address); in setup_serial_console()
30 if (uart->baud) { in setup_serial_console()
31 p += sprintf(p, ",%llu", uart->baud); in setup_serial_console()
32 if (uart->bits) { in setup_serial_console()
33 switch (uart->parity) { in setup_serial_console()
38 p += sprintf(p, "%c%d", parity, uart->bits); in setup_serial_console()
42 add_preferred_console("uart", 8250, &options[9]); in setup_serial_console()
87 struct pcdp_uart *uart; in efi_setup_pcdp_console() local
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