| /Linux-v6.1/drivers/gpu/drm/tegra/ |
| D | mipi-phy.c | 16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
24 timing->clktermen = 0; in mipi_dphy_timing_get_default()
25 timing->clktrail = 80; in mipi_dphy_timing_get_default()
26 timing->clkzero = 260; in mipi_dphy_timing_get_default()
27 timing->dtermen = 0; in mipi_dphy_timing_get_default()
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| /Linux-v6.1/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy.c | 28 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
46 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
47 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
50 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing, in msm_dsi_dphy_timing_calc() argument
72 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true); in msm_dsi_dphy_timing_calc()
76 timing->hs_rqst = temp; in msm_dsi_dphy_timing_calc()
78 timing->hs_rqst = max_t(s32, 0, temp - 2); in msm_dsi_dphy_timing_calc()
81 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2); in msm_dsi_dphy_timing_calc()
86 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true); in msm_dsi_dphy_timing_calc()
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| D | dsi_phy_20nm.c | 11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
16 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero)); in dsi_20nm_dphy_set_timing()
18 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail)); in dsi_20nm_dphy_set_timing()
20 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare)); in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
25 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit)); in dsi_20nm_dphy_set_timing()
27 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero)); in dsi_20nm_dphy_set_timing()
29 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare)); in dsi_20nm_dphy_set_timing()
31 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail)); in dsi_20nm_dphy_set_timing()
33 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst)); in dsi_20nm_dphy_set_timing()
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| /Linux-v6.1/drivers/clk/tegra/ |
| D | clk-tegra124-emc.c | 48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
120 struct emc_timing *timing = NULL; in emc_determine_rate() local
136 timing = tegra->timings + i; in emc_determine_rate()
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
154 if (timing) { in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
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| /Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | timing.c | 26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
51 return timing; in nvbios_timingTe()
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| /Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 43 struct intf_timing_params *timing) in drm_mode_to_intf_timing_params() argument
45 memset(timing, 0, sizeof(*timing)); in drm_mode_to_intf_timing_params()
72 timing->width = mode->hdisplay; /* active width */ in drm_mode_to_intf_timing_params()
73 timing->height = mode->vdisplay; /* active height */ in drm_mode_to_intf_timing_params()
74 timing->xres = timing->width; in drm_mode_to_intf_timing_params()
75 timing->yres = timing->height; in drm_mode_to_intf_timing_params()
76 timing->h_back_porch = mode->htotal - mode->hsync_end; in drm_mode_to_intf_timing_params()
77 timing->h_front_porch = mode->hsync_start - mode->hdisplay; in drm_mode_to_intf_timing_params()
78 timing->v_back_porch = mode->vtotal - mode->vsync_end; in drm_mode_to_intf_timing_params()
79 timing->v_front_porch = mode->vsync_start - mode->vdisplay; in drm_mode_to_intf_timing_params()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_optc.c | 42 bool optc201_is_two_pixels_per_containter(const struct dc_crtc_timing *timing) in optc201_is_two_pixels_per_containter() argument
44 return optc1_is_two_pixels_per_containter(timing); in optc201_is_two_pixels_per_containter()
77 const struct dc_crtc_timing *timing) in optc201_validate_timing() argument
84 ASSERT(timing != NULL); in optc201_validate_timing()
86 v_blank = (timing->v_total - timing->v_addressable - in optc201_validate_timing()
87 timing->v_border_top - timing->v_border_bottom); in optc201_validate_timing()
89 h_blank = (timing->h_total - timing->h_addressable - in optc201_validate_timing()
90 timing->h_border_right - in optc201_validate_timing()
91 timing->h_border_left); in optc201_validate_timing()
93 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE && in optc201_validate_timing()
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| /Linux-v6.1/drivers/video/fbdev/ |
| D | gbefb.c | 37 struct gbe_timing_info timing; member
410 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
416 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
418 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
426 timing->pll_m = 4; in gbefb_setup_flatpanel()
427 timing->pll_n = 1; in gbefb_setup_flatpanel()
428 timing->pll_p = 0; in gbefb_setup_flatpanel()
455 struct gbe_timing_info *timing) in compute_gbe_timing() argument
466 /* Determine valid resolution and timing in compute_gbe_timing()
502 /* set video timing information */ in compute_gbe_timing()
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| /Linux-v6.1/drivers/video/fbdev/via/ |
| D | via_modesetting.c | 18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
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| /Linux-v6.1/drivers/memory/tegra/ |
| D | tegra124-emc.c | 516 /* Timing change sequence functions */
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
577 struct emc_timing *timing = NULL; in tegra_emc_find_timing() local
582 timing = &emc->timings[i]; in tegra_emc_find_timing()
587 if (!timing) { in tegra_emc_find_timing()
588 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
592 return timing; in tegra_emc_find_timing()
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change() local
606 if (!timing) in tegra_emc_prepare_timing_change()
609 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) in tegra_emc_prepare_timing_change()
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| D | tegra30-emc.c | 409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
440 struct emc_timing *timing = NULL; in emc_find_timing() local
445 timing = &emc->timings[i]; in emc_find_timing()
450 if (!timing) { in emc_find_timing()
451 dev_err(emc->dev, "no timing for rate %lu\n", rate); in emc_find_timing()
455 return timing; in emc_find_timing()
458 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
464 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { in emc_dqs_preset()
475 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { in emc_dqs_preset()
486 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { in emc_dqs_preset()
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| /Linux-v6.1/drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 122 struct awg_timing *timing) in awg_generate_line_signal() argument
127 if (timing->trailing_pixels > 0) { in awg_generate_line_signal()
129 val = timing->blanking_level; in awg_generate_line_signal()
132 val = timing->trailing_pixels - 1 + AWG_DELAY; in awg_generate_line_signal()
137 val = timing->blanking_level; in awg_generate_line_signal()
138 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
141 if (timing->blanking_pixels > 0) { in awg_generate_line_signal()
143 val = timing->active_pixels - 1; in awg_generate_line_signal()
147 val = timing->blanking_level; in awg_generate_line_signal()
156 struct awg_timing *timing) in sti_awg_generate_code_data_enable_mode() argument
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_timing_generator_v.c | 45 * DCE11 Timing Generator Implementation
243 const struct dc_crtc_timing *timing) in dce110_timing_generator_v_program_blanking() argument
245 uint32_t vsync_offset = timing->v_border_bottom + in dce110_timing_generator_v_program_blanking()
246 timing->v_front_porch; in dce110_timing_generator_v_program_blanking()
247 uint32_t v_sync_start = timing->v_addressable + vsync_offset; in dce110_timing_generator_v_program_blanking()
249 uint32_t hsync_offset = timing->h_border_right + in dce110_timing_generator_v_program_blanking()
250 timing->h_front_porch; in dce110_timing_generator_v_program_blanking()
251 uint32_t h_sync_start = timing->h_addressable + hsync_offset; in dce110_timing_generator_v_program_blanking()
262 timing->h_total - 1, in dce110_timing_generator_v_program_blanking()
271 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
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| D | dce110_timing_generator.c | 55 * So we can create dce110 timing generator to use it.
67 struct dc_crtc_timing *timing) in dce110_timing_generator_apply_front_porch_workaround() argument
69 if (timing->flags.INTERLACE == 1) { in dce110_timing_generator_apply_front_porch_workaround()
70 if (timing->v_front_porch < 2) in dce110_timing_generator_apply_front_porch_workaround()
71 timing->v_front_porch = 2; in dce110_timing_generator_apply_front_porch_workaround()
73 if (timing->v_front_porch < 1) in dce110_timing_generator_apply_front_porch_workaround()
74 timing->v_front_porch = 1; in dce110_timing_generator_apply_front_porch_workaround()
121 * Enable CRTC - call ASIC Control Object to enable Timing generator.
230 * disable_crtc - call ASIC Control Object to disable Timing generator.
256 const struct dc_crtc_timing *timing) in program_horz_count_by_2() argument
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| /Linux-v6.1/drivers/media/rc/img-ir/ |
| D | img-ir-hw.h | 22 /* Timing information */
53 * struct img_ir_timing_range - range of timing values
54 * @min: Minimum timing value
55 * @max: Maximum timing value (if < @min, this will be set to @min during
65 * struct img_ir_symbol_timing - timing data for a symbol
66 * @pulse: Timing range for the length of the pulse in this symbol
67 * @space: Timing range for the length of the space in this symbol
75 * struct img_ir_free_timing - timing data for free time symbol
88 * struct img_ir_timings - Timing values.
89 * @ldr: Leader symbol timing data
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| /Linux-v6.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramnv50.c | 34 #include <subdev/bios/timing.h>
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dsc/ |
| D | dc_dsc.c | 56 const struct dc_crtc_timing *timing,
61 const struct dc_crtc_timing *timing,
81 const struct dc_crtc_timing *timing,
339 * timing's pixel clock and uncompressed bandwidth.
348 const struct dc_crtc_timing *timing, in dc_dsc_compute_bandwidth_range() argument
356 get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); in dc_dsc_compute_bandwidth_range()
359 timing->pixel_encoding, &dsc_common_caps); in dc_dsc_compute_bandwidth_range()
362 is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing, in dc_dsc_compute_bandwidth_range()
367 config.num_slices_h, &dsc_common_caps, timing, range); in dc_dsc_compute_bandwidth_range()
470 const struct dc_crtc_timing *timing, in compute_bpp_x16_from_target_bandwidth() argument
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| /Linux-v6.1/drivers/ata/ |
| D | pata_triflex.c | 62 * triflex_load_timing - timing configuration
76 u32 timing = 0; in triflex_load_timing() local
88 timing = 0x0103;break; in triflex_load_timing()
90 timing = 0x0203;break; in triflex_load_timing()
92 timing = 0x0808;break; in triflex_load_timing()
96 timing = 0x0F0F;break; in triflex_load_timing()
98 timing = 0x0202;break; in triflex_load_timing()
100 timing = 0x0204;break; in triflex_load_timing()
102 timing = 0x0404;break; in triflex_load_timing()
104 timing = 0x0508;break; in triflex_load_timing()
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| /Linux-v6.1/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 63 description: Output tap delay for SD/MMC legacy timing
69 description: Output tap delay for MMC high speed timing
75 description: Output tap delay for SD high speed timing
81 description: Output tap delay for SD UHS SDR12 timing
87 description: Output tap delay for SD UHS SDR25 timing
93 description: Output tap delay for SD UHS SDR50 timing
99 description: Output tap delay for SD UHS SDR104 timing
105 description: Output tap delay for SD UHS DDR50 timing
111 description: Output tap delay for eMMC DDR52 timing
117 description: Output tap delay for eMMC HS200 timing
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| D | sdhci-sprd.txt | 33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
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| /Linux-v6.1/Documentation/driver-api/memory-devices/ |
| D | ti-gpmc.rst | 20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
50 custom timing routines, a kind of reverse engineering without
52 in mainline having custom timing routine) and by simulation.
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_timing_generator.c | 100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
109 timing->v_border_top - timing->v_border_bottom) * in dce120_timing_generator_validate_timing()
115 timing, in dce120_timing_generator_validate_timing()
121 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()
122 timing->v_sync_width < tg110->min_v_sync_width) in dce120_timing_generator_validate_timing()
129 const struct dc_crtc_timing *timing) in dce120_tg_validate_timing() argument
131 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_hwseq.c | 77 bool hblank_halved = optc2_is_two_pixels_per_containter(&stream->timing); in calc_mpc_flow_ctrl_cnt()
83 flow_ctrl_cnt = stream->timing.h_total - stream->timing.h_addressable - in calc_mpc_flow_ctrl_cnt()
84 stream->timing.h_border_left - in calc_mpc_flow_ctrl_cnt()
85 stream->timing.h_border_right; in calc_mpc_flow_ctrl_cnt()
114 …dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.… in update_dsc_on_stream()
115 …dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v… in update_dsc_on_stream()
116 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; in update_dsc_on_stream()
117 dsc_cfg.color_depth = stream->timing.display_color_depth; in update_dsc_on_stream()
119 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; in update_dsc_on_stream()
188 …rol_2x_pclk = (pipe_ctx->stream->timing.flags.INTERLACE || optc2_is_two_pixels_per_containter(&pip… in dcn314_update_odm()
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| /Linux-v6.1/drivers/media/i2c/ |
| D | bt819.c | 60 struct timing { struct
70 static struct timing timing_data[] = { argument
164 0x16, 0x07, /* 0x16 Video Timing Polarity in bt819_init()
175 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
178 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_init()
179 (((timing->vactive >> 8) & 0x03) << 4) | in bt819_init()
180 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_init()
181 ((timing->hactive >> 8) & 0x03); in bt819_init()
182 init[0x04 * 2 - 1] = timing->vdelay & 0xff; in bt819_init()
183 init[0x05 * 2 - 1] = timing->vactive & 0xff; in bt819_init()
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| /Linux-v6.1/drivers/gpu/drm/mediatek/ |
| D | mtk_dsi.c | 233 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig() local
235 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1; in mtk_dsi_phy_timconfig()
236 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000; in mtk_dsi_phy_timconfig()
237 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 - in mtk_dsi_phy_timconfig()
238 timing->da_hs_prepare; in mtk_dsi_phy_timconfig()
239 timing->da_hs_trail = timing->da_hs_prepare + 1; in mtk_dsi_phy_timconfig()
241 timing->ta_go = 4 * timing->lpx - 2; in mtk_dsi_phy_timconfig()
242 timing->ta_sure = timing->lpx + 2; in mtk_dsi_phy_timconfig()
243 timing->ta_get = 4 * timing->lpx; in mtk_dsi_phy_timconfig()
244 timing->da_hs_exit = 2 * timing->lpx + 1; in mtk_dsi_phy_timconfig()
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