Searched full:tegra186_clk_pll_a_out0 (Results 1 – 3 of 3) sorted by relevance
192 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;294 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;308 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;322 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;334 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;346 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;358 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;[all …]
95 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
93 * @def TEGRA186_CLK_PLL_A_OUT0712 #define TEGRA186_CLK_PLL_A_OUT0 246 macro
