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/Linux-v5.15/Documentation/networking/devlink/
Ddevlink-dpipe.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ``devlink-dpipe`` provides a standardized way to provide visibility into the
34 Level Path Compression trie (LPC-trie) in hardware.
36 In many situations trying to analyze systems failure solely based on the
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
50 configuration, but the ``devlink-dpipe`` interface uses it for visibility
52 ``devlink-dpipe`` should change according to the changes done by the
56 using Ternary Content Addressable Memory (TCAM). The TCAM memory can be
57 divided into TCAM regions. Complex TC filters can have multiple rules with
59 TCAM regions have a predefined lookup key. Offloading the TC filter rules
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/Linux-v5.15/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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/Linux-v5.15/arch/arm64/
DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
12 bool "Allwinner sunxi 64-bit SoC Family"
21 This enables support for Allwinner sunxi based SoCs like the A64.
34 This enables support for Apple's in-house ARM SoC family, starting
57 BCM49408 SoCs. These SoCs use Brahma-B53 cores and can be
66 This enables support for Broadcom iProc based SoCs
83 bool "Broadcom Set-Top-Box SoCs"
93 bool "ARMv8 based Samsung Exynos SoC family"
104 This enables support for ARMv8 based Samsung Exynos SoC family.
107 bool "ARMv8 based Microchip Sparx5 SoC family"
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/Linux-v5.15/Documentation/devicetree/bindings/net/
Dmicrochip,sparx5-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
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/Linux-v5.15/drivers/net/ethernet/intel/ice/
Dice_flex_pipe.c1 // SPDX-License-Identifier: GPL-2.0
85 * ice_sect_id - returns section ID
109 hdr = (struct ice_buf_hdr *)buf->buf; in ice_pkg_val_buf()
111 section_count = le16_to_cpu(hdr->section_count); in ice_pkg_val_buf()
115 data_end = le16_to_cpu(hdr->data_end); in ice_pkg_val_buf()
133 (ice_seg->device_table + in ice_find_buf_table()
134 le32_to_cpu(ice_seg->device_table_count)); in ice_find_buf_table()
137 (nvms->vers + le32_to_cpu(nvms->table_count)); in ice_find_buf_table()
146 * call is made with the ice_seg parameter non-NULL; on subsequent calls,
156 state->buf_table = ice_find_buf_table(ice_seg); in ice_pkg_enum_buf()
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/Linux-v5.15/net/dsa/
Dtag_ocelot_8021q.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2020-2021 NXP
4 * An implementation of the software-defined tag_8021q.c tagger format, which
6 * this by using the TCAM engines for:
7 * - pushing the RX VLAN as a second, outer tag, on egress towards the CPU port
8 * - redirecting towards the correct front port based on TX VLAN and popping
19 struct felix_port *felix_port = dp->priv; in ocelot_defer_xmit()
26 kthread_init_work(&xmit_work->work, felix_port->xmit_work_fn); in ocelot_defer_xmit()
30 xmit_work->dp = dp; in ocelot_defer_xmit()
31 xmit_work->skb = skb_get(skb); in ocelot_defer_xmit()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 tristate "Tag driver for Atheros AR9331 SoC with built-in switch"
25 the Atheros AR9331 SoC with built-in switch.
32 tristate "Tag driver for Broadcom switches using in-frame headers"
39 tristate "Tag driver for Broadcom legacy switches using in-frame headers"
109 hardware-defined injection/extraction frame header. Flow control
117 custom VLAN-based header. Frames that require timestamping, such as
118 PTP, are not delivered over Ethernet but over register-based MMIO.
120 this mode, less TCAM resources (VCAP IS1, IS2, ES0) are available for
121 use with tc-flower.
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/Linux-v5.15/drivers/net/ethernet/mscc/
Docelot_vcap.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
23 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */
24 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */
40 u32 tg_sw; /* Current type-group */
45 u32 tg_value; /* Current type-group value */
46 u32 tg_mask; /* Current type-group mask */
52 return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL); in vcap_read_update_ctrl()
62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count) in vcap_cmd()
74 ocelot_target_write(ocelot, vcap->target, value, VCAP_CORE_UPDATE_CTRL); in vcap_cmd()
81 /* Convert from 0-based row to VCAP entry row and run command */
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/Linux-v5.15/drivers/net/ethernet/mellanox/mlxsw/
Dreg.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
72 /* SMID - Switch Multicast ID
73 * --------------------------
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/Linux-v5.15/Documentation/devicetree/bindings/powerpc/fsl/
Dinterlaken-lac.txt2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
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/Linux-v5.15/drivers/net/ethernet/freescale/dpaa2/
Ddpni.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2016 Freescale Semiconductor Inc.
20 * DPNI_MAX_TC - Maximum number of traffic classes
24 * DPNI_MAX_DPBP - Maximum number of buffer pools per DPNI
29 * DPNI_ALL_TCS - All traffic classes considered; see dpni_set_queue()
31 #define DPNI_ALL_TCS (u8)(-1)
33 * DPNI_ALL_TC_FLOWS - All flows within traffic class considered; see
36 #define DPNI_ALL_TC_FLOWS (u16)(-1)
38 * DPNI_NEW_FLOW_ID - Generate new flow ID; see dpni_set_queue()
40 #define DPNI_NEW_FLOW_ID (u16)(-1)
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/Linux-v5.15/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2.h1 /* SPDX-License-Identifier: GPL-2.0 */
355 /* Packet Processor per-port counters */
420 /* Per-port registers */
485 /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
486 * relative to port->base.
522 /* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
526 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
596 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
714 /* Maximum number of T-CONTs of PON port */
754 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
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/Linux-v5.15/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_filter.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
65 return -ENOMEM; in set_tcb_field()
69 req->reply_ctrl = htons(REPLY_CHAN_V(0) | in set_tcb_field()
70 QUEUENO_V(adap->sge.fw_evtq.abs_id) | in set_tcb_field()
72 req->word_cookie = htons(TCB_WORD_V(word) | TCB_COOKIE_V(ftid)); in set_tcb_field()
73 req->mask = cpu_to_be64(mask); in set_tcb_field()
74 req->val = cpu_to_be64(val); in set_tcb_field()
75 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); in set_tcb_field()
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Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
110 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
127 #define FW4_CFNAME "cxgb4/t4-config.txt"
128 #define FW5_CFNAME "cxgb4/t5-config.txt"
129 #define FW6_CFNAME "cxgb4/t6-config.txt"
145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
159 * offset by 2 bytes in order to have the IP headers line up on 4-byte
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Dt4_hw.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
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/Linux-v5.15/drivers/net/ethernet/chelsio/cxgb4vf/
Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
82 * the PCI-E SR-IOV standard).
91 MODULE_PARM_DESC(msi, "whether to use MSI-X or MSI");
112 * list entries are 64-bit PCI DMA addresses. And since the state of
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/Linux-v5.15/drivers/net/dsa/sja1105/
Dsja1105_dynamic_config.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 /* In the dynamic configuration interface, the switch exposes a register-like
13 * This file creates a per-switch-family abstraction called
15 * - sja1105_dynamic_config_write
16 * - sja1105_dynamic_config_read
25 * +-----------------------------------------+------------------+
27 * +-----------------------------------------+------------------+
29 * <----------------------- packed_size ------------------------>
33 * function is reused (bar exceptional cases - see
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Dsja1105_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
19 #include <linux/pcs/pcs-xpcs.h>
62 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; in sja1105_is_vlan_configured()
63 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; in sja1105_is_vlan_configured()
70 return -1; in sja1105_is_vlan_configured()
75 struct sja1105_private *priv = ds->priv; in sja1105_drop_untagged()
78 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_drop_untagged()
93 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_pvid_apply()
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/Linux-v5.15/drivers/scsi/csiostor/
Dcsio_hw.c4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
64 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
65 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
66 {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
67 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
68 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
69 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
70 {"T540-CH 10G", "Chelsio T540-CH 10G [FCoE]"},
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/Linux-v5.15/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
389 { OUTER_DST_MAC, 48, KEY_OPT_MAC, -1, -1 },
390 { OUTER_SRC_MAC, 48, KEY_OPT_MAC, -1, -1 },
391 { OUTER_VLAN_TAG_FST, 16, KEY_OPT_LE16, -1, -1 },
392 { OUTER_VLAN_TAG_SEC, 16, KEY_OPT_LE16, -1, -1 },
393 { OUTER_ETH_TYPE, 16, KEY_OPT_LE16, -1, -1 },
394 { OUTER_L2_RSV, 16, KEY_OPT_LE16, -1, -1 },
395 { OUTER_IP_TOS, 8, KEY_OPT_U8, -1, -1 },
396 { OUTER_IP_PROTO, 8, KEY_OPT_U8, -1, -1 },
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