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/Linux-v5.10/Documentation/networking/devlink/
Ddevlink-dpipe.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ``devlink-dpipe`` provides a standardized way to provide visibility into the
34 Level Path Compression trie (LPC-trie) in hardware.
36 In many situations trying to analyze systems failure solely based on the
45 The ``devlink-dpipe`` interface closes this gap. The hardware's pipeline is
50 configuration, but the ``devlink-dpipe`` interface uses it for visibility
52 ``devlink-dpipe`` should change according to the changes done by the
56 using Ternary Content Addressable Memory (TCAM). The TCAM memory can be
57 divided into TCAM regions. Complex TC filters can have multiple rules with
59 TCAM regions have a predefined lookup key. Offloading the TC filter rules
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/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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/Linux-v5.10/arch/arm64/
DKconfig.platforms1 # SPDX-License-Identifier: GPL-2.0-only
17 bool "Allwinner sunxi 64-bit SoC Family"
23 This enables support for Allwinner sunxi based SoCs like the A64.
52 This enables support for Broadcom iProc based SoCs
69 bool "Broadcom Set-Top-Box SoCs"
79 bool "ARMv8 based Samsung Exynos SoC family"
90 This enables support for ARMv8 based Samsung Exynos SoC family.
93 bool "ARMv8 based Microchip Sparx5 SoC family"
97 This enables support for the Microchip Sparx5 ARMv8-based
98 SoC family of TSN-capable gigabit switches.
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/Linux-v5.10/drivers/net/ethernet/intel/ice/
Dice_flex_pipe.c1 // SPDX-License-Identifier: GPL-2.0
85 * ice_sect_id - returns section ID
109 hdr = (struct ice_buf_hdr *)buf->buf; in ice_pkg_val_buf()
111 section_count = le16_to_cpu(hdr->section_count); in ice_pkg_val_buf()
115 data_end = le16_to_cpu(hdr->data_end); in ice_pkg_val_buf()
133 (ice_seg->device_table + in ice_find_buf_table()
134 le32_to_cpu(ice_seg->device_table_count)); in ice_find_buf_table()
137 (nvms->vers + le32_to_cpu(nvms->table_count)); in ice_find_buf_table()
146 * call is made with the ice_seg parameter non-NULL; on subsequent calls,
156 state->buf_table = ice_find_buf_table(ice_seg); in ice_pkg_enum_buf()
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/Linux-v5.10/drivers/net/ethernet/mscc/
Docelot_vcap.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
23 VCAP_CMD_WRITE = 0, /* Copy from Cache to TCAM */
24 VCAP_CMD_READ = 1, /* Copy from TCAM to Cache */
40 u32 tg_sw; /* Current type-group */
45 u32 tg_value; /* Current type-group value */
46 u32 tg_mask; /* Current type-group mask */
52 return ocelot_target_read(ocelot, vcap->target, VCAP_CORE_UPDATE_CTRL); in vcap_read_update_ctrl()
62 if ((sel & VCAP_SEL_ENTRY) && ix >= vcap->entry_count) in vcap_cmd()
74 ocelot_target_write(ocelot, vcap->target, value, VCAP_CORE_UPDATE_CTRL); in vcap_cmd()
81 /* Convert from 0-based row to VCAP entry row and run command */
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/Linux-v5.10/drivers/net/ethernet/mellanox/mlxsw/
Dreg.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
72 /* SMID - Switch Multicast ID
73 * --------------------------
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/Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dinterlaken-lac.txt2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
7 - Example LAC Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
10 - Example LAC SWP Node with Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
17 The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
18 facilitate interoperability between a data path device and a look-aside
19 co-processor, the Interlaken Look-Aside protocol is defined for short
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/Linux-v5.10/drivers/net/ethernet/freescale/dpaa2/
Ddpni.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2016 Freescale Semiconductor Inc.
32 #define DPNI_ALL_TCS (u8)(-1)
36 #define DPNI_ALL_TC_FLOWS (u16)(-1)
40 #define DPNI_NEW_FLOW_ID (u16)(-1)
56 * Allocate policers for this DPNI. They can be used to rate-limit traffic per
69 * Enables TCAM for Flow Steering and QoS look-ups. If not specified, all
70 * look-ups are exact match. Note that TCAM is not available on LS1088 and its
93 * struct dpni_pools_cfg - Structure representing buffer pools configuration
185 * struct dpni_attr - Structure representing DPNI attributes
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/Linux-v5.10/drivers/net/ethernet/marvell/mvpp2/
Dmvpp2.h1 /* SPDX-License-Identifier: GPL-2.0 */
346 /* Packet Processor per-port counters */
407 /* Per-port registers */
472 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
473 * relative to port->base.
509 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */
513 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
583 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
692 /* Maximum number of T-CONTs of PON port */
729 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
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/Linux-v5.10/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_filter.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
65 return -ENOMEM; in set_tcb_field()
69 req->reply_ctrl = htons(REPLY_CHAN_V(0) | in set_tcb_field()
70 QUEUENO_V(adap->sge.fw_evtq.abs_id) | in set_tcb_field()
72 req->word_cookie = htons(TCB_WORD_V(word) | TCB_COOKIE_V(ftid)); in set_tcb_field()
73 req->mask = cpu_to_be64(mask); in set_tcb_field()
74 req->val = cpu_to_be64(val); in set_tcb_field()
75 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); in set_tcb_field()
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Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
110 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
127 #define FW4_CFNAME "cxgb4/t4-config.txt"
128 #define FW5_CFNAME "cxgb4/t5-config.txt"
129 #define FW6_CFNAME "cxgb4/t6-config.txt"
145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
159 * offset by 2 bytes in order to have the IP headers line up on 4-byte
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Dt4_hw.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
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/Linux-v5.10/drivers/net/ethernet/chelsio/cxgb4vf/
Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
82 * the PCI-E SR-IOV standard).
91 MODULE_PARM_DESC(msi, "whether to use MSI-X or MSI");
112 * list entries are 64-bit PCI DMA addresses. And since the state of
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/Linux-v5.10/drivers/net/dsa/sja1105/
Dsja1105_dynamic_config.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
6 /* In the dynamic configuration interface, the switch exposes a register-like
13 * This file creates a per-switch-family abstraction called
15 * - sja1105_dynamic_config_write
16 * - sja1105_dynamic_config_read
25 * +-----------------------------------------+------------------+
27 * +-----------------------------------------+------------------+
29 * <----------------------- packed_size ------------------------>
33 * function is reused (bar exceptional cases - see
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Dsja1105_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
68 * Every queue i holds top[i] - base[i] frames. in sja1105_init_mac_settings()
69 * Sum of top[i] - base[i] is 511 (max hardware limit). in sja1105_init_mac_settings()
80 /* No static correction for 1-step 1588 events */ in sja1105_init_mac_settings()
92 /* Don't drop double-tagged traffic */ in sja1105_init_mac_settings()
98 /* Disable learning and I/O on user ports by default - in sja1105_init_mac_settings()
109 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG]; in sja1105_init_mac_settings()
112 if (table->entry_count) { in sja1105_init_mac_settings()
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/Linux-v5.10/drivers/scsi/csiostor/
Dcsio_hw.c4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
64 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
65 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
66 {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
67 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
68 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
69 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
70 {"T540-CH 10G", "Chelsio T540-CH 10G [FCoE]"},
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/Linux-v5.10/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
424 u64 *data = (u64 *)(&hdev->mac_stats); in hclge_mac_update_stats_defective()
431 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); in hclge_mac_update_stats_defective()
433 dev_err(&hdev->pdev->dev, in hclge_mac_update_stats_defective()
461 u64 *data = (u64 *)(&hdev->mac_stats); in hclge_mac_update_stats_complete()
472 return -ENOMEM; in hclge_mac_update_stats_complete()
475 ret = hclge_cmd_send(&hdev->hw, desc, desc_num); in hclge_mac_update_stats_complete()
511 ret = hclge_cmd_send(&hdev->hw, &desc, 1); in hclge_mac_query_reg_num()
518 *desc_num = 1 + ((reg_num - 3) >> 2) + in hclge_mac_query_reg_num()
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