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/Linux-v6.6/arch/mips/kernel/
Dcps-vec-ns16550.S34 * @t9: UART base address
37 1: UART_L t0, UART_LSR_OFS(t9)
40 UART_S a0, UART_TX_OFS(t9)
47 * @t9: UART base address
67 * @t9: UART base address
84 * @t9: UART base address
101 * @t9: UART base address
118 * @t9: UART base address
137 * @t9: UART base address
176 li t9, CKSEG1ADDR(CONFIG_MIPS_CPS_NS16550_BASE)
Dcps-vec.S171 move a1, t9
302 * struct vpe_boot_config in v1, VPE ID in t9
314 li t9, 0
323 mfc0 t9, CP0_GLOBALNUMBER
324 andi t9, t9, MIPS_GLOBALNUMBER_VP
343 mfc0 t9, $15, 1
344 and t9, t9, t1
349 mul v1, t9, t1
Docteon_switch.S48 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
53 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
65 LONG_L t9, TASK_STACK_CANARY(a1)
66 LONG_S t9, 0(t8)
99 dmfc0 t9, $9,7 /* CvmCtl register. */
108 bbit1 t9, 28, 1f
116 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
262 dmfc0 t9, $9,7 /* CvmCtl register. */
273 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
283 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
Dr2300_switch.S40 LONG_L t9, TASK_STACK_CANARY(a1)
41 LONG_S t9, 0(t8)
Dr4k_switch.S36 LONG_L t9, TASK_STACK_CANARY(a1)
37 LONG_S t9, 0(t8)
/Linux-v6.6/arch/mips/boot/compressed/
Dhead.S35 PTR_LA t9, decompress_kernel
36 jalr t9
43 PTR_LI t9, KERNEL_ENTRY
44 jalr t9
/Linux-v6.6/arch/mips/include/asm/mach-loongson64/
Dkernel-entry-init.h81 /* a0:base t1:cpuid t2:node t9:count */
93 2: li t9, 0x100 /* wait for init loop */
94 3: addiu t9, -1 /* limit mailbox access */
95 bnez t9, 3b
/Linux-v6.6/tools/perf/util/hisi-ptt-decoder/
Dhisi-ptt-pkt-decoder.c36 * DW0 [ Fmt ][ Type ][T9][T8][TH][SO][ Length ][ Time ]
80 uint32_t t9 : 1; member
138 "Format", dw0.format, "Type", dw0.type, "T9", dw0.t9, in hisi_ptt_4dw_print_dw0()
/Linux-v6.6/arch/mips/mm/
Dpage.c47 #define T9 25 macro
109 uasm_i_lui(buf, T9, uasm_rel_hi(off)); in pg_addiu()
110 uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off)); in pg_addiu()
112 uasm_i_addiu(buf, T9, ZERO, off); in pg_addiu()
113 uasm_i_daddu(buf, reg1, reg2, T9); in pg_addiu()
116 uasm_i_lui(buf, T9, uasm_rel_hi(off)); in pg_addiu()
117 uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off)); in pg_addiu()
118 UASM_i_ADDU(buf, reg1, reg2, T9); in pg_addiu()
/Linux-v6.6/arch/alpha/lib/
Dstxcpy.S13 * t9 = return address
39 .frame sp, 0, t9
91 ret (t9) # .. e1 :
99 .frame sp, 0, t9
230 ret (t9) # .. e1 :
288 ret (t9) # e1 :
Dev6-stxcpy.S13 * t9 = return address
50 .frame sp, 0, t9
109 ret (t9) # L0 : Latency=3
119 .frame sp, 0, t9
259 ret (t9) # L0 : Latency=3
318 ret (t9) # e1 :
Dstxncpy.S14 * t9 = return address
47 .frame sp, 0, t9, 0
105 ret (t9) # e1 :
118 .frame sp, 0, t9, 0
266 ret (t9) # .. e1 :
344 ret (t9) # .. e1 :
Dev6-stxncpy.S14 * t9 = return address
58 .frame sp, 0, t9, 0
133 ret (t9) # L0 : Latency=3
150 .frame sp, 0, t9, 0
312 ret (t9) # L0 : Latency=3
393 ret (t9) # L0 : Latency=3
Dstacktrace.c43 "a2 ", "a3 ", "a4 ", "a5 ", "t8 ", "t9 ", "t10", "t11", "ra ",
/Linux-v6.6/arch/ia64/lib/
Dcopy_page_mck.S53 * | n[y] | t9 | | (L2 cache line)
84 #define t9 t5 // alias! macro
163 (p[D]) ld8 t9 = [src0], 3*8
170 (p[D]) st8 [dst0] = t9, 3*8
/Linux-v6.6/arch/arm64/crypto/
Dghash-ce-core.S31 t9 .req v16
106 pmull\t t9.8h, \ad, \b4\().\nb // K = A*B4
115 uzp1 t6.2d, t7.2d, t9.2d
116 uzp2 t7.2d, t7.2d, t9.2d
124 // t9 = (K) (P6 + P7) << 32
133 zip2 t9.2d, t6.2d, t7.2d
139 ext t9.16b, t9.16b, t9.16b, #12
142 eor t7.16b, t7.16b, t9.16b
Dcrct10dif-ce-core.S89 t9 .req v23
145 pmull t9.8h, ad.8b, bd3.8b // I = A*B3
159 pmull2 t9.8h, ad.16b, bd3.16b // I = A*B3
164 eor t6.16b, t6.16b, t9.16b // N = I + J
/Linux-v6.6/arch/mips/include/asm/
Dregdef.h51 #define t9 $25 macro
94 #define t9 $25 /* callee address for PIC/temp */ macro
/Linux-v6.6/drivers/gpu/drm/i915/display/
Dintel_pps.c1288 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1308 drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", in intel_pps_dump_state()
1310 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
1322 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || in intel_pps_verify_state()
1332 return delays->t1_t3 || delays->t8 || delays->t9 || in pps_delays_valid()
1394 spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ in pps_init_delays_spec()
1428 assign_final(t9); in pps_init_delays()
1436 intel_dp->pps.backlight_off_delay = get_delay(t9); in pps_init_delays()
1453 * on them. For T8, even BSpec recommends doing it. For T9, if we in pps_init_delays()
1459 final->t9 = 1; in pps_init_delays()
[all …]
/Linux-v6.6/arch/mips/vdso/
DMakefile67 # Check that we don't have PIC 'jalr t9' calls left
69 cmd_vdso_mips_check = if $(OBJDUMP) --disassemble $@ | grep -E -h "jalr.*t9" > /dev/null; \
70 then (echo >&2 "$@: PIC 'jalr t9' calls are not supported"; \
/Linux-v6.6/arch/mips/kvm/
Dentry.c46 #define T9 25 macro
320 UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd); in kvm_mips_build_enter_guest()
321 uasm_i_jalr(&p, RA, T9); in kvm_mips_build_enter_guest()
701 UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd); in kvm_mips_build_exit()
702 uasm_i_jalr(&p, RA, T9); in kvm_mips_build_exit()
770 UASM_i_LA(&p, T9, (unsigned long)kvm_mips_handle_exit); in kvm_mips_build_exit()
771 uasm_i_jalr(&p, RA, T9); in kvm_mips_build_exit()
/Linux-v6.6/arch/alpha/include/uapi/asm/
Dregdef.h33 #define t9 $23 macro
/Linux-v6.6/arch/arm64/boot/dts/mediatek/
Dmt8192-asurada-spherion-r0.dts42 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
Dmt8192-asurada-hayato-r1.dts24 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
/Linux-v6.6/arch/arm64/boot/dts/qcom/
Dsc7180-trogdor-pazquel360.dtsi47 MATRIX_KEY(0x01, 0x09, 0) /* T9 */

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