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/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dqcom,gcc-sc8280xp.yaml33 - description: Primary USB SuperSpeed pipe clock
41 - description: Secondary USB SuperSpeed pipe clock
49 - description: Multiport USB first SuperSpeed pipe clock
50 - description: Multiport USB second SuperSpeed pipe clock
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dqcom,usb-ss.yaml7 title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
13 Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
30 - description: SuperSpeed pipe clock
/Linux-v6.1/arch/mips/cavium-octeon/
Docteon-usb.c28 /* Reference clock select for SuperSpeed and HighSpeed PLLs:
31 * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
33 * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
58 /* Enable reference clock to prescaler for SuperSpeed functionality.
107 /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
115 /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
416 /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ in dwc3_octeon_clocks_start()
419 /* Step 5c: Enable SuperSpeed. */ in dwc3_octeon_clocks_start()
/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dnvidia,tegra-xudc.yaml11 USB 3.0 SuperSpeed protocols.
78 - description: XUSBA(superspeed) power-domain
Ddwc3-cavium.txt1 Cavium SuperSpeed DWC3 USB SoC controller
Dti,hd3ss3220.yaml13 HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel
Drockchip,dwc3.yaml7 title: Rockchip SuperSpeed DWC3 USB SoC controller
Ddwc3-xilinx.yaml7 title: Xilinx SuperSpeed DWC3 USB SoC controller
/Linux-v6.1/drivers/thunderbolt/
Dacpi.c41 * bound so the USB3 SuperSpeed ports are not yet created. in tb_acpi_add_link()
56 * SuperSpeed ports have this property and they are not power in tb_acpi_add_link()
57 * managed with the xHCI and the SuperSpeed hub so we create the in tb_acpi_add_link()
/Linux-v6.1/drivers/usb/core/
Dport.c444 * may miss a suspend event for the SuperSpeed port. in link_peers()
461 * The SuperSpeed reference is dropped when the HiSpeed port in in link_peers()
463 * SuperSpeed connection to drop since there is no risk of a in link_peers()
499 * usb_port_runtime_resume() event which takes a SuperSpeed ref in unlink_peers()
517 /* Drop the SuperSpeed ref held on behalf of the active HiSpeed port */ in unlink_peers()
/Linux-v6.1/Documentation/driver-api/usb/
Dusb3-debug-port.rst75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
143 [ 79.454780] usb 2-2.1: new SuperSpeed USB device number 3 using xhci_hcd
Dpower-management.rst655 another hub. The expectation is that all superspeed ports have a
662 peer ports are simply the hi-speed and superspeed interface pins that
666 While a superspeed port is powered off a device may downgrade its
671 before their superspeed peer is permitted to power-off. The implication is
672 that the setting ``pm_qos_no_power_off`` to zero on a superspeed port may
675 if it wants to guarantee that a superspeed port will power-off.
677 2. Port resume is sequenced to force a superspeed port to power-on prior to its
Ddwc3.rst2 Synopsys DesignWare Core SuperSpeed USB 3.0 Controller
11 The *Synopsys DesignWare Core SuperSpeed USB 3.0 Controller*
12 (hereinafter referred to as *DWC3*) is a USB SuperSpeed compliant
41 your IP team and/or *Synopsys DesignWare Core SuperSpeed USB 3.0
53 7. SuperSpeed Bulk Streams
89 to a value that's divisible by *wMaxPacketSize* (1024 on SuperSpeed,
Dbulk-streams.rst47 SuperSpeed device will say how many stream IDs it can handle. Therefore,
/Linux-v6.1/include/linux/usb/
Dgadget.h216 * @comp_desc: In case of SuperSpeed support, this is the endpoint companion
344 * @ssp_rate: Current connected SuperSpeed Plus signaling rate and lane count.
345 * @max_ssp_rate: Maximum SuperSpeed Plus signaling rate and lane count the UDC
417 /* USB SuperSpeed Plus only */
564 * gadget_is_superspeed() - return true if the hardware handles superspeed
565 * @g: controller that might support superspeed
574 * superspeed plus
575 * @g: controller that might support superspeed plus
Dch9.h38 /* USB 3.2 SuperSpeed Plus phy signaling rate generation and lane count */
/Linux-v6.1/drivers/phy/samsung/
Dphy-exynos5-usbdrd.c275 * clock settings for SuperSpeed operations.
613 * SuperSpeed requirements on Exynos5420 and Exynos5800 systems,
635 "Failed setting Loss-of-Signal level for SuperSpeed\n"); in exynos5420_usbdrd_phy_calibrate()
649 "Failed setting Tx-Vboost-Level for SuperSpeed\n"); in exynos5420_usbdrd_phy_calibrate()
681 "Fail to set RxDet measurement time for SuperSpeed\n"); in exynos5420_usbdrd_phy_calibrate()
/Linux-v6.1/arch/arm64/boot/dts/amlogic/
Dmeson-g12b-a311d-khadas-vim3.dts20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
Dmeson-g12b-s922x-khadas-vim3.dts20 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
Dmeson-sm1-khadas-vim3l.dts88 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
/Linux-v6.1/drivers/usb/mtu3/
DKconfig13 Dual Role SuperSpeed USB controller. You can select usb
/Linux-v6.1/Documentation/ABI/testing/
Dsysfs-driver-typec-displayport47 USB SuperSpeed protocol. From user perspective pin assignments C
/Linux-v6.1/drivers/phy/broadcom/
DKconfig31 driver. It supports all versions of Superspeed and
/Linux-v6.1/drivers/usb/host/
Dpci-quirks.c1035 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
1037 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
1083 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n", in usb_enable_intel_xhci_ports()
1086 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable in usb_enable_intel_xhci_ports()
1087 * Register, to turn on SuperSpeed terminations for the in usb_enable_intel_xhci_ports()
/Linux-v6.1/drivers/usb/dwc3/
DKconfig9 Say Y or M here if your system has a Dual Role SuperSpeed

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