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/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dspi-sifive.yaml4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-spi
22 - sifive,fu740-c000-spi
23 - const: sifive,spi0
26 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Unlike most other PWM controllers, the SiFive PWM controller currently
22 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
31 - sifive,fu540-c000-pwm
32 - sifive,fu740-c000-pwm
33 - const: sifive,pwm0
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/dma/
Dsifive,fu540-c000-pdma.yaml4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 - sifive,fu540-c000-pdma
33 - const: sifive,pdma0
35 Should be "sifive,<chip>-pdma" and "sifive,pdma<version>".
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
7 title: SiFive Core Local Interruptor
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
28 - sifive,fu540-c000-clint
31 - const: sifive,clint0
33 - const: sifive,clint0
39 Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
41 "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
42 onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
44 "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/serial/
Dsifive-serial.yaml4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
24 - const: sifive,uart0
27 Should be something similar to "sifive,<chip>-uart"
29 and "sifive,uart<version>" for the general UART IP
[all …]
/Linux-v6.1/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi2 /* Copyright (c) 2018-2019 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
181 compatible = "sifive,fu540-c000-prci";
[all …]
Dfu740-c000.dtsi2 /* Copyright (c) 2020 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
11 compatible = "sifive,fu740-c000", "sifive,fu740";
26 compatible = "sifive,bullet0", "riscv";
42 compatible = "sifive,bullet0", "riscv";
66 compatible = "sifive,bullet0", "riscv";
90 compatible = "sifive,bullet0", "riscv";
114 compatible = "sifive,bullet0", "riscv";
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
182 compatible = "sifive,fu740-c000-prci";
[all …]
Dhifive-unleashed-a00.dts2 /* Copyright (c) 2018-2019 SiFive, Inc */
13 model = "SiFive HiFive Unleashed A00";
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
15 "sifive,fu540";
/Linux-v6.1/Documentation/devicetree/bindings/sifive/
Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/riscv/
Dsifive,ccache0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
8 title: SiFive Composable Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 The SiFive Composable Cache Controller is used to provide access to fast copies
25 - sifive,ccache0
26 - sifive,fu540-c000-ccache
27 - sifive,fu740-c000-ccache
37 - sifive,ccache0
[all …]
Dsifive.yaml4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
23 - sifive,hifive-unleashed-a00
24 - const: sifive,fu540-c000
25 - const: sifive,fu540
29 - sifive,hifive-unmatched-a00
30 - const: sifive,fu740-c000
[all …]
Dcpus.yaml10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
31 - sifive,rocket0
32 - sifive,bullet0
33 - sifive,e5
34 - sifive,e7
35 - sifive,e71
36 - sifive,u74-mc
37 - sifive,u54
38 - sifive,u74
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/gpio/
Dsifive,gpio.yaml4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
7 title: SiFive GPIO controller
10 - Paul Walmsley <paul.walmsley@sifive.com>
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
19 - const: sifive,gpio0
44 It is 16 for the SiFive SoCs and 32 for the Canaan K210.
69 - sifive,fu540-c000-gpio
70 - sifive,fu740-c000-gpio
79 #include <dt-bindings/clock/sifive-fu540-prci.h>
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
48 - Sagar Kadam <sagar.kadam@sifive.com>
49 - Paul Walmsley <paul.walmsley@sifive.com>
61 - sifive,fu540-c000-plic
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/clock/sifive/
Dfu540-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
18 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
27 const: sifive,fu540-c000-prci
56 compatible = "sifive,fu540-c000-prci";
Dfu740-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml#
8 title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI)
11 - Zong Li <zong.li@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
18 macros defined in include/dt-bindings/clock/sifive-fu740-prci.h.
27 const: sifive,fu740-c000-prci
59 compatible = "sifive,fu740-c000-prci";
/Linux-v6.1/arch/riscv/
DKconfig.erratas4 bool "SiFive errata"
8 All SiFive errata Kconfig depend on this Kconfig. Disabling
9 this Kconfig will disable all SiFive errata. Please say "Y"
10 here if your platform uses SiFive CPU cores.
15 bool "Apply SiFive errata CIP-453"
19 This will apply the SiFive CIP-453 errata to add sign extension
26 bool "Apply SiFive errata CIP-1200"
30 This will apply the SiFive CIP-1200 errata to repalce all
/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dsifive,fu740-pcie.yaml4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
7 title: SiFive FU740 PCIe host controller
10 SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
24 const: sifive,fu740-pcie
87 #include <dt-bindings/clock/sifive-fu740-prci.h>
90 compatible = "sifive,fu740-pcie";
/Linux-v6.1/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi18 compatible = "sifive,e51", "sifive,rocket0", "riscv";
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
188 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
200 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
224 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
/Linux-v6.1/drivers/tty/serial/
Dsifive.c3 * SiFive UART driver
5 * Copyright (C) 2018-2019 SiFive
12 * - drivers/pwm/pwm-sifive.c
16 * SiFive FE310-G000 v2p3
18 * https://github.com/sifive/sifive-blocks/
20 * The SiFive UART design is not 8250-compatible. The following common
117 #define SIFIVE_SERIAL_NAME "sifive-serial"
119 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
145 * Configuration data specific to this SiFive UART.
178 * __ssp_early_writel() - write to a SiFive serial port register (early)
[all …]
/Linux-v6.1/drivers/edac/
Dsifive_edac.c3 * SiFive Platform EDAC Driver
5 * Copyright (C) 2018-2022 SiFive, Inc.
13 #include <soc/sifive/sifive_ccache.h>
61 p->dci->mod_name = "Sifive ECC Manager"; in ecc_register()
117 MODULE_AUTHOR("SiFive Inc.");
118 MODULE_DESCRIPTION("SiFive platform EDAC driver");
/Linux-v6.1/drivers/clk/sifive/
DKconfig4 bool "SiFive SoC driver support"
8 SoC drivers for SiFive Linux-capable SoCs.
13 bool "PRCI driver for SiFive SoCs"
20 FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
Dfu540-prci.h3 * Copyright (C) 2018-2021 SiFive, Inc.
8 * The FU540 PRCI implements clock and reset control for the SiFive
16 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
25 #include <dt-bindings/clock/sifive-fu540-prci.h>
27 #include "sifive-prci.h"
/Linux-v6.1/drivers/spi/
Dspi-sifive.c3 // Copyright 2018 SiFive, Inc.
5 // SiFive SPI controller driver (master mode only)
7 // Author: SiFive, Inc.
8 // sifive@sifive.com
330 of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth", in sifive_spi_probe()
336 of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word", in sifive_spi_probe()
469 { .compatible = "sifive,spi0", },
485 MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
486 MODULE_DESCRIPTION("SiFive SPI driver");
/Linux-v6.1/drivers/soc/sifive/
Dsifive_ccache.c3 * SiFive composable cache controller Driver
5 * Copyright (C) 2018-2022 SiFive, Inc.
18 #include <soc/sifive/sifive_ccache.h>
107 { .compatible = "sifive,fu540-c000-ccache" },
108 { .compatible = "sifive,fu740-c000-ccache" },
109 { .compatible = "sifive,ccache0" },

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