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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dti,phy-am654-serdes.yaml4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
7 title: TI AM654 SERDES binding
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
19 - ti,phy-am654-serdes
26 - const: serdes
46 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
48 ti,serdes-clk:
49 description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
57 description: Phandle to the SYSCON entry required for configuring SERDES lane function.
61 - description: Clock output names for SERDES 0
[all …]
Dmscc,vsc7514-serdes.yaml4 $id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
7 title: Microsemi Ocelot SerDes muxing
15 space for setting up the SerDes to switch port muxing.
17 A SerDes X can be "muxed" to work with switch port Y or Z for example.
18 One specific SerDes can also be used as a PCIe interface.
20 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
22 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
35 - mscc,vsc7514-serdes
40 The first number defines the input port to use for a given SerDes macro.
42 dt-bindings/phy/phy-ocelot-serdes.h
[all …]
Dmicrochip,sparx5-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
7 title: Microchip Sparx5 Serdes controller
13 The Sparx5 SERDES interfaces share the same basic functionality, but
16 The following list lists the SERDES features:
31 The SERDES6G is a high-speed SERDES interface, which can operate at
41 The SERDES10G is a high-speed SERDES interface, which can operate at
54 The SERDES25G is a high-speed SERDES interface, which can operate at
67 pattern: "^serdes@[0-9a-f]+$"
70 const: microchip,sparx5-serdes
78 - The main serdes input port
[all …]
Dmicrochip,lan966x-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
7 title: Microchip Lan966x Serdes controller
16 interfaces. The Serdes controller will allow to configure these interfaces
23 interface SerDes 2.
27 pattern: "^serdes@[0-9a-f]+$"
30 const: microchip,lan966x-serdes
42 dt-bindings/phy/phy-lan966x-serdes.
53 serdes: serdes@e2004010 {
54 compatible = "microchip,lan966x-serdes";
Dti,phy-j721e-wiz.yaml8 title: TI J721E WIZ (SERDES Wrapper)
71 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
125 the SERDES.
152 provided by the SERDES.
167 "^serdes@[0-9a-f]+$":
170 WIZ node should have '1' subnode for the SERDES. It could be either
171 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
174 Torrent SERDES should follow the bindings specified in
249 serdes@5000000 {
251 reg-names = "serdes";
/Linux-v6.1/arch/arm64/boot/dts/microchip/
Dsparx5_pcb135_board.dtsi377 phys = <&serdes 13>;
384 phys = <&serdes 13>;
391 phys = <&serdes 13>;
398 phys = <&serdes 13>;
405 phys = <&serdes 14>;
412 phys = <&serdes 14>;
419 phys = <&serdes 14>;
426 phys = <&serdes 14>;
433 phys = <&serdes 15>;
440 phys = <&serdes 15>;
[all …]
Dsparx5_pcb134_board.dtsi719 phys = <&serdes 13>;
729 phys = <&serdes 14>;
738 phys = <&serdes 15>;
747 phys = <&serdes 16>;
756 phys = <&serdes 17>;
765 phys = <&serdes 18>;
774 phys = <&serdes 19>;
783 phys = <&serdes 20>;
792 phys = <&serdes 21>;
801 phys = <&serdes 22>;
[all …]
/Linux-v6.1/arch/arm64/boot/dts/amd/
Damd-seattle-xgbe-b.dtsi40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
48 amd,serdes-blwc = <1>, <1>, <0>;
49 amd,serdes-cdr-rate = <2>, <2>, <7>;
50 amd,serdes-pq-skew = <10>, <10>, <18>;
51 amd,serdes-tx-amp = <0>, <0>, <0>;
52 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
53 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
66 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Damd-xgbe.txt8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
43 - amd,serdes-blwc: Baseline wandering correction enablement
46 - amd,serdes-cdr-rate: CDR rate speed selection
47 - amd,serdes-pq-skew: PQ (data sampling) skew
48 - amd,serdes-tx-amp: TX amplitude boost
49 - amd,serdes-dfe-tap-config: DFE taps available to run
50 - amd,serdes-dfe-tap-enable: DFE taps to enable
70 amd,serdes-blwc = <1>, <1>, <0>;
[all …]
Dhisilicon-hns-dsaf.txt17 The second region is SerDes base register and size(optional, only used when
18 serdes-syscon in port node does not exist). It is recommended using
19 serdes-syscon rather than this address.
40 - serdes-syscon: is syscon handle for SerDes register.
81 serdes-syscon = <&serdes>;
87 serdes-syscon = <&serdes>;
Dmicrochip,sparx5-switch.yaml97 phandle of a Ethernet SerDes PHY. This defines which SerDes
157 phys = <&serdes 13>;
166 phys = <&serdes 29>;
175 phys = <&serdes 30>;
184 phys = <&serdes 31>;
193 phys = <&serdes 32>;
203 phys = <&serdes 0>;
/Linux-v6.1/arch/arm/boot/dts/
Dlan966x-pcb8290.dts11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
104 phys = <&serdes 0 SERDES6G(1)>;
112 phys = <&serdes 1 SERDES6G(1)>;
120 phys = <&serdes 2 SERDES6G(1)>;
128 phys = <&serdes 3 SERDES6G(1)>;
136 phys = <&serdes 4 SERDES6G(2)>;
144 phys = <&serdes 5 SERDES6G(2)>;
152 phys = <&serdes 6 SERDES6G(2)>;
160 phys = <&serdes 7 SERDES6G(2)>;
164 &serdes {
Dlan966x-kontron-kswitch-d10-mmt.dtsi8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
128 phys = <&serdes 0 CU(0)>;
135 phys = <&serdes 1 CU(1)>;
142 phys = <&serdes 4 SERDES6G(2)>;
149 phys = <&serdes 5 SERDES6G(2)>;
156 phys = <&serdes 6 SERDES6G(2)>;
163 phys = <&serdes 7 SERDES6G(2)>;
169 &serdes {
Dlan966x-pcb8309.dts7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
169 phys = <&serdes 0 CU(0)>;
176 phys = <&serdes 1 CU(1)>;
184 phys = <&serdes 2 SERDES6G(0)>;
192 phys = <&serdes 3 SERDES6G(1)>;
196 &serdes {
/Linux-v6.1/drivers/phy/mscc/
Dphy-ocelot-serdes.c3 * SerDes PHY driver for Microsemi Ocelot
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
60 static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode) in serdes_init_s6g() argument
89 ret = serdes_update_mcb_s6g(regmap, serdes); in serdes_init_s6g()
146 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
222 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
230 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
244 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
292 static int serdes_init_s1g(struct regmap *regmap, u8 serdes) in serdes_init_s1g() argument
296 ret = serdes_update_mcb_s1g(regmap, serdes); in serdes_init_s1g()
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-pcie-msm8996.c192 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
233 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
245 void __iomem *serdes; member
384 void __iomem *serdes = qphy->serdes; in qmp_pcie_msm8996_serdes_init() local
391 qmp_pcie_msm8996_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num); in qmp_pcie_msm8996_serdes_init()
393 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET); in qmp_pcie_msm8996_serdes_init()
394 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL], in qmp_pcie_msm8996_serdes_init()
397 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS]; in qmp_pcie_msm8996_serdes_init()
415 void __iomem *serdes = qphy->serdes; in qmp_pcie_msm8996_com_init() local
447 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL], in qmp_pcie_msm8996_com_init()
[all …]
/Linux-v6.1/drivers/net/ethernet/sfc/
Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/Linux-v6.1/drivers/net/ethernet/sfc/falcon/
Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/Linux-v6.1/drivers/net/ethernet/sfc/siena/
Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/Linux-v6.1/drivers/phy/microchip/
DKconfig7 tristate "Microchip Sparx5 SerDes PHY driver"
13 Enable this for support of the 10G/25G SerDes on Microchip Sparx5.
16 tristate "SerDes PHY driver for Microchip LAN966X"
21 Enable this for supporting SerDes muxing with Microchip LAN966X
/Linux-v6.1/drivers/phy/marvell/
DKconfig36 shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
55 shared serdes PHYs on Marvell Armada 38x. Its serdes lanes can be
66 shared serdes PHYs on Marvell Armada 7k/8k (in the CP110). Its serdes
/Linux-v6.1/drivers/phy/ti/
DKconfig25 tristate "TI AM654 SERDES support"
33 This option enables support for TI AM654 SerDes PHY used for
37 tristate "TI J721E WIZ (SERDES Wrapper) support"
47 SoC. WIZ is a serdes wrapper used to configure some of the input
48 signals to the SERDES (Sierra/Torrent). This driver configures
/Linux-v6.1/drivers/net/dsa/mv88e6xxx/
Dserdes.c3 * Marvell 88E6xxx SERDES manipulation, via SMI bus
18 #include "serdes.h"
202 dev_err(chip->dev, "can't read Serdes PHY BMSR: %d\n", err); in mv88e6352_serdes_pcs_get_state()
208 dev_err(chip->dev, "can't read Serdes PHY status: %d\n", err); in mv88e6352_serdes_pcs_get_state()
214 dev_err(chip->dev, "can't read Serdes PHY LPA: %d\n", err); in mv88e6352_serdes_pcs_get_state()
378 dev_err(chip->dev, "can't read Serdes BMSR: %d\n", err); in mv88e6352_serdes_irq_link()
471 /* The serdes power can't be controlled on this switch chip but we need in mv88e6185_serdes_power()
480 /* There are no configurable serdes lanes on this switch chip but we in mv88e6185_serdes_get_lane()
482 * mv88e6xxx_serdes_get_lane() know this is a serdes port. in mv88e6185_serdes_get_lane()
535 /* The serdes interrupts are enabled in the G2_INT_MASK register. We in mv88e6097_serdes_irq_enable()
[all …]
/Linux-v6.1/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
99 phys = <&serdes 4 SERDES1G(2)>;
106 phys = <&serdes 5 SERDES1G(5)>;
113 phys = <&serdes 6 SERDES1G(3)>;
120 phys = <&serdes 9 SERDES1G(4)>;
/Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-intel.h11 /* SERDES Register */
16 /* SERDES defines */
19 #define SERDES_RST BIT(2) /* Serdes Reset */
20 #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/

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