Searched full:smmuv3 (Results 1 – 15 of 15) sorted by relevance
7 title: Arm SMMUv3 Performance Monitor Counter Group14 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
7 title: ARM SMMUv3 Architecture Implementation14 The SMMUv3 architecture is a significant departure from previous
388 tristate "ARM Ltd. System MMU Version 3 (SMMUv3) Support"398 the ARM SMMUv3 architecture.401 bool "Shared Virtual Addressing support for the ARM SMMUv3"407 SMMUv3.
94 tristate "ARM SMMUv3 Performance Monitors Extension"98 Provides support for the ARM SMMUv3 Performance Monitor Counter
5 * Monitor Counter Groups (PMCG) associated with an SMMUv3 node8 * SMMUv3 PMCG devices are named as smmuv3_pmcg_<phys_addr_page> where740 flags, "smmuv3-pmu", pmu); in smmu_pmu_setup_irq()981 MODULE_DESCRIPTION("PMU driver for ARM SMMUv3 Performance Monitors Extension");
22 #define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */
413 * SMMUv3 dev ID mapping index was introduced in revision 1 in iort_get_id_mapping_index()1451 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_count_resources()1473 * irq line. Use single irq line for all the SMMUv3 interrupts. in arm_smmu_v3_is_combined_irq()1505 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_init_resources()1549 /* Retrieve SMMUv3 specific data */ in arm_smmu_v3_dma_configure()1555 /* We expect the dma masks to be equivalent for all SMMUv3 set-ups */ in arm_smmu_v3_dma_configure()1564 * set numa proximity domain for smmuv3 device
3 * IOMMU API for ARM architected SMMUv3 implementations.617 /* An SMMUv3 instance */
3 * Implementation of the IOMMU SVA API for the ARM SMMUv3
3 * IOMMU API for ARM architected SMMUv3 implementations.3243 * lines. Use a single irq line for all the SMMUv3 interrupts. in arm_smmu_setup_irqs()3650 /* Retrieve SMMUv3 specific data */ in arm_smmu_device_acpi_probe()3885 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMUv3 implementations");
320 * of HiSilicon platforms hip06/hip07 to support the SMMUv3326 * ARM SMMUv3 driver requires a quirk to treat the MSI regions
1151 * of HiSilicon platforms hip06/hip07 to support the SMMUv31157 * ARM SMMUv3 driver requires a quirk to treat the MSI regions
507 u64 base_address; /* SMMUv3 base address */522 #define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */523 #define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* hi_silicon Hi161x SMMUv3 */524 #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */
161 | Cavium | ThunderX2 SMMUv3| #74 | N/A |163 | Cavium | ThunderX2 SMMUv3| #126 | N/A |
900 * The PTT device is supposed to behind an ARM SMMUv3, which
