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/Linux-v5.15/Documentation/devicetree/bindings/clock/
Dqcom,gcc-sm6125.yaml4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
7 title: Qualcomm Global Clock & Reset Controller Binding for SM6125
14 power domains on SM6125.
17 - dt-bindings/clock/qcom,gcc-sm6125.h
21 const: qcom,gcc-sm6125
64 compatible = "qcom,gcc-sm6125";
Dqcom,rpmcc.txt31 "qcom,rpmcc-sm6125", "qcom,rpmcc"
/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dqcom,sm6125-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-pinctrl.yaml#
6 title: Qualcomm Technologies, Inc. SM6125 TLMM block
13 in the SM6125 platform.
20 const: qcom,sm6125-tlmm
51 - $ref: "#/$defs/qcom-sm6125-tlmm-state"
54 $ref: "#/$defs/qcom-sm6125-tlmm-state"
57 qcom-sm6125-tlmm-state:
121 compatible = "qcom,sm6125-tlmm";
/Linux-v5.15/arch/arm64/boot/dts/qcom/
Dsm6125.dtsi6 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
158 compatible = "qcom,scm-sm6125", "qcom,scm";
298 compatible = "qcom,rpm-sm6125";
302 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc";
327 compatible = "qcom,sm6125-tlmm";
361 compatible = "qcom,gcc-sm6125";
389 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
407 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
483 compatible = "qcom,sm6125-apcs-hmss-global";
Dsm6125-sony-xperia-seine-pdx201.dts8 #include "sm6125.dtsi"
15 qcom,msm-id = <394 0x10000>; /* sm6125 v1 */
19 compatible = "sony,pdx201", "qcom,sm6125";
DMakefile86 dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
/Linux-v5.15/Documentation/devicetree/bindings/mailbox/
Dqcom,apcs-kpss-global.yaml32 - qcom,sm6125-apcs-hmss-global
82 - qcom,sm6125-apcs-hmss-global
/Linux-v5.15/drivers/clk/qcom/
Dclk-smd-rpm.c974 /* SM6125 */
975 DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
976 DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
977 DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk,
979 DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0);
980 DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0);
981 DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1);
982 DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk,
984 DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk,
1085 { .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 },
DMakefile85 obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
DKconfig559 tristate "SM6125 Global Clock Controller"
561 Support for the global clock controller on SM6125 devices.
Dgcc-sm6125.c16 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
4132 { .compatible = "qcom,gcc-sm6125" },
4172 .name = "gcc-sm6125",
4189 MODULE_DESCRIPTION("QTI GCC SM6125 Driver");
/Linux-v5.15/drivers/pinctrl/qcom/
DKconfig278 tristate "Qualcomm Technologies Inc SM6125 pin controller driver"
284 Technologies Inc SM6125 platform.
DMakefile35 obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o
Dpinctrl-sm6125.c1250 { .compatible = "qcom,sm6125-tlmm", },
1256 .name = "sm6125-tlmm",
1275 MODULE_DESCRIPTION("QTI sm6125 TLMM driver");
/Linux-v5.15/Documentation/devicetree/bindings/soc/qcom/
Dqcom,smd-rpm.yaml43 - qcom,rpm-sm6125
/Linux-v5.15/drivers/mailbox/
Dqcom-apcs-ipc-mailbox.c175 { .compatible = "qcom,sm6125-apcs-hmss-global", .data = &sm6125_apcs_data },
/Linux-v5.15/drivers/soc/qcom/
Dsmd-rpm.c246 { .compatible = "qcom,rpm-sm6125" },
Dsocinfo.c296 { 394, "SM6125" },
/Linux-v5.15/drivers/iommu/arm/arm-smmu/
Darm-smmu-qcom.c411 { .compatible = "qcom,sm6125-smmu-500" },