Home
last modified time | relevance | path

Searched full:slc (Results 1 – 25 of 53) sorted by relevance

123

/Linux-v6.1/drivers/gpu/drm/amd/amdkfd/
Dcwsr_trap_handler_gfx10.asm374 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] slc:1 glc:1
406 global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] inst_offset:0x40 slc:1 glc:1
453 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
455 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128
456 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*2
457 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3
466 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
468 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
469 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
470 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
[all …]
Dcwsr_trap_handler_gfx8.asm352 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
353 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
354 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
355 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
407 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1
450 buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1
451 buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256
452 buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*2
453 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
547 buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1
[all …]
Dcwsr_trap_handler_gfx9.asm559 buffer_store_dwordx2 v[0:1], v2, s_save_buf_rsrc0, s_save_mem_offset offen:1 glc:1 slc:1
957 buffer_store_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
958 buffer_store_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256
959 buffer_store_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2
960 buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
964 buffer_load_dword v0, v0, s_rsrc, s_mem_offset slc:1 glc:1
965 buffer_load_dword v1, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256
966 buffer_load_dword v2, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*2
967 buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
/Linux-v6.1/include/uapi/linux/genwqe/
Dgenwqe_card.h89 * SLC: Queue Virtual Window Window for accessing into a specific VF
98 /* SLC: Queue Segment */
102 /* SLC: Queue Offset */
106 /* SLC: Queue Configuration */
110 /* SLC: Job Timout/Only accessible for the PF */
116 /* SLC: Queue InitSequence Register */
120 /* SLC: Queue Wrap */
124 /* SLC: Queue Status */
128 /* SLC: Queue Working Time */
132 /* SLC: Queue Error Counts */
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mtd/
Dlpc32xx-slc.txt1 NXP LPC32xx SoC NAND SLC controller
4 - compatible: "nxp,lpc3220-slc"
27 slc: flash@20020000 {
28 compatible = "nxp,lpc3220-slc";
/Linux-v6.1/arch/arm/mach-lpc32xx/
Dphy3250.c21 .bus_id = "nand-slc",
22 .min_signal = 1, /* SLC NAND Flash */
65 OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
/Linux-v6.1/drivers/mtd/nand/raw/
Dnand_toshiba.c158 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per in toshiba_nand_decode_id()
159 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as in toshiba_nand_decode_id()
163 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC in toshiba_nand_decode_id()
174 * For Toshiba SLC, ecc requrements are as follows: in toshiba_nand_decode_id()
Dlpc32xx_slc.c3 * NXP LPC32XX NAND SLC driver
34 * SLC NAND controller register offsets
74 #define SLCSTAT_SLC_FIFO (1 << 1) /* SLC FIFO has data bit */
241 /* Reset SLC controller */ in lpc32xx_nand_setup()
251 /* Get base clock for SLC block */ in lpc32xx_nand_setup()
326 * Prepares SLC for transfers with H/W ECC enabled
733 "nand-slc"); in lpc32xx_nand_dma_setup()
896 /* NAND callbacks for LPC32xx SLC hardware */ in lpc32xx_nand_probe()
1016 { .compatible = "nxp,lpc3220-slc" },
1037 MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX SLC controller");
Dnand_esmt.c45 * It is known that some ESMT SLC NANDs have been shipped in esmt_nand_init()
DKconfig166 tristate "NXP LPC32xx SLC NAND controller"
170 Enables support for NXP's LPC32XX SLC (i.e. for Single Level Cell
175 by the SLC NAND controller.
Dnand_amd.c40 * According to the datasheet of some Cypress SLC NANDs, in amd_nand_init()
/Linux-v6.1/Documentation/devicetree/bindings/mtd/partitions/
Dpartition.yaml49 slc-mode:
50 description: This parameter, if present, allows one to emulate SLC mode
/Linux-v6.1/drivers/mtd/parsers/
Dcmdlinepart.c12 * <partdef> := <size>[@<offset>][<name>][ro][lk][slc]
156 /* if slc is found use emulated SLC mode on this partition*/ in newpart()
157 if (!strncmp(s, "slc", 3)) { in newpart()
/Linux-v6.1/drivers/crypto/cavium/nitrox/
Dnitrox_reqmgr.c474 sr->instr.slc.value[0] = 0; in nitrox_process_se_request()
475 sr->instr.slc.s.ssz = sr->out.sgmap_cnt; in nitrox_process_se_request()
476 sr->instr.slc.bev[0] = cpu_to_be64(sr->instr.slc.value[0]); in nitrox_process_se_request()
479 sr->instr.slc.s.rptr = cpu_to_be64(sr->out.sgcomp_dma); in nitrox_process_se_request()
Dnitrox_hal.c168 /* step 1: disable slc port */ in reset_pkt_solicit_port()
184 /* step 3: clear slc counters */ in reset_pkt_solicit_port()
285 * This includes NPS packet in and slc interrupts.
293 /* NPS packet slc port interrupts */ in enable_nps_pkt_interrupts()
/Linux-v6.1/arch/arc/mm/
Dcache.c57 p = &cpuinfo_arc700[c].slc; in arc_cache_mumbojumbo()
60 "SLC\t\t: %uK, %uB Line%s\n", in arc_cache_mumbojumbo()
77 struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc; in read_decode_cache_bcr_arcv2()
588 * SLC is shared between all cores and concurrent aux operations from in slc_op_rgn()
651 * SLC is shared between all cores and concurrent aux operations from in slc_op_line()
1066 * 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
1093 /* Flush + invalidate SLC */ in arc_ioc_setup()
1194 /* Note that SLC disable not formally supported till HS 3.0 */ in arc_cache_init_master()
1211 * In case of IOC (say IOC+SLC case), pointers above could still be set in arc_cache_init_master()
/Linux-v6.1/include/linux/mtd/
Dlpc32xx_slc.h3 * Platform data for LPC32xx SoC SLC NAND controller
Donenand_regs.h102 /* Note: It's actually 0x3f in case of SLC */
115 /* Note: It's actually 0x03 in case of SLC */
/Linux-v6.1/arch/arm/boot/dts/
Dlpc3250-phy3250.dts149 /* 64MB Flash via SLC NAND controller */
150 &slc {
Dlpc3250-ea3250.dts215 /* 128MB Flash via SLC NAND controller */
216 &slc {
Dlpc32xx.dtsi63 * Enable either SLC or MLC
65 slc: flash@20020000 { label
66 compatible = "nxp,lpc3220-slc";
/Linux-v6.1/arch/x86/
DKconfig.cpu14 AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2,
23 SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
58 AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5S.
/Linux-v6.1/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,ifc.yaml16 external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
/Linux-v6.1/include/uapi/mtd/
Dmtd-abi.h145 #define MTD_NANDFLASH 4 /* SLC NAND */
154 #define MTD_SLC_ON_MLC_EMULATION 0x4000 /* Emulate SLC behavior on MLC NANDs */
/Linux-v6.1/arch/m68k/include/asm/
Dmachines.h67 #define SM_4C_SLC 0x04 /* Sun4c SparcStation SLC - Sun 4/20 */

123